A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption
| dc.contributor.author | Lad, K. | |
| dc.contributor.author | Bhat, M.S. | |
| dc.date.accessioned | 2026-02-06T06:40:10Z | |
| dc.date.issued | 2013 | |
| dc.description.abstract | A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. © 2013 IEEE. | |
| dc.identifier.citation | 2013 International Conference on Computer Communication and Informatics, ICCCI 2013, 2013, Vol., , p. - | |
| dc.identifier.uri | https://doi.org/10.1109/ICCCI.2013.6466320 | |
| dc.identifier.uri | https://idr.nitk.ac.in/handle/123456789/32744 | |
| dc.subject | Fat tree encoder | |
| dc.subject | Flash ADC | |
| dc.subject | Low power | |
| dc.subject | Preamplifier based latch comparator | |
| dc.title | A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption |