LR-Based Performance Evaluation of MoCs

Abstract

In the recent decade, on-chip communication net-works have developed into a potent platform for tackling chal-lenging and significant computation issues. However, many applications cannot achieve high-performance communication needs due to the seamless integration of computing cores in systems-on-chip (SoCs). Subsequently, a network-on-chip (NoC) has emerged as a prominent on-chip communication infrastructure in SoCs. Performance analysis of NoC's is essential for its architectural design and is traditionally evaluated employing a simulator. How-ever, simulation-based performance evaluation is relatively slow and may take a long time with varying architectural NoC sizes. This paper presents an AI-based approach for investigating mesh-based NoC (MoC) performance over the traditional simulation-based performance evaluation. The proposed framework targets to reach two objectives- quickly and accurately evaluation of various NoC performance metrics. Simulations are performed at varying architectural setups on a set of mesh NoCs to generate the training dataset for the proposed framework. Consequently, the framework satisfactorily predicts different performance metrics. For example, network and packet latency; hop count; switch, channel, and total power consumption; and total area are in the range of 58.14-88.49 and 58.69-106.97 cycles; 6.231-6.257; 1.44-13.02, 13.73-129.06, and 25.26- 177.44 μ W; and 1.35874 μ m2, respectively while the proposed framework is applied on the 9 x 9 mesh NoC. The metrics are with 94% accuracy and predicted at very significantly less time. The LR model saves 99.45 % evaluation time resulting in the speedup of 260 x than a simulation - based method. © 2024 IEEE.