Impact of process variation induced transistor mismatch on sense amplifier performance
| dc.contributor.author | Rodrigues, S. | |
| dc.contributor.author | Bhat, M.S. | |
| dc.date.accessioned | 2020-03-30T10:18:16Z | |
| dc.date.available | 2020-03-30T10:18:16Z | |
| dc.date.issued | 2006 | |
| dc.description.abstract | Sense amplifier is a very critical peripheral circuit in memories as its performance strongly affects both memory access time, and overall memory power dissipation. As the device dimensions scale below 100nm, the process variations are increasing and are impacting the circuit design significantly. The circuit yield loss caused by the process and device parameter variation has been more pronounced than before [1]. In this paper, effects of process variation induced transistor mismatch on sense amplifier performance are studied. A comparative study of the effect of mismatch on delay and yield for different sense amplifier configurations at 90nm technology is presented. � 2006 IEEE. | en_US |
| dc.identifier.citation | Proceedings - 2006 14th International Conference on Advanced Computing and Communications, ADCOM 2006, 2006, Vol., , pp.497-502 | en_US |
| dc.identifier.uri | https://idr.nitk.ac.in/handle/123456789/8247 | |
| dc.title | Impact of process variation induced transistor mismatch on sense amplifier performance | en_US |
| dc.type | Book chapter | en_US |
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