Software verification using state diagrams

Abstract

During the development of software, a programmer will commit many logical errors unknowingly such that the software is not in accordance with the requirements. Such logical errors affect the correctness of the software. The requirements specify some important properties of the software and this knowledge about it will allow to know the behavior of the software which can be leveraged to find certain logical errors. This paper proposes a method which helps to find bugs as well as describes a way by which the programmer can specify software requirements. Based on these programmer specified requirements, the system can be automatically used to verify the software. Also, the method proposed in this paper does not need to use the expected result of a test case to verify the software’s correctness. The proposed algorithm completely relies on the requirements specified by the programmer for finding bugs in the software. The software verification process and the algorithm used is explained with the help of a case study. The paper highlights the advantages of the method and algorithm proposed for software verification along with the implementation details. © Grenze Scientific Society, 2021.