Energy Efficient Inductor-Less High Speed Phase Locked Loop

Abstract

The advancement in integrated circuit technology has resulted in easier implementation of many systems on a single chip. This modern system on chip (SoC) demands multiple phase locked loop (PLL) systems for high speed clock generation, clock and data recovery, IO links, local oscillators for transceivers, power management etc. PLL designs with low power consumption and small size are more crucial for battery operated devices. This research mainly focuses on implementing energy e cient, small area, high speed PLL. Literature lists many PFD designs that will either have blind zone/dead zone e ect or have smaller linear range. In this work, a high speed deadzone-free zero blind-zone phase frequency detector is proposed that of- fers a wide linear range. This circuit is designed using UMC 65nm CMOS technology. Achieved maximum frequency of operation is 3.44 GHz which is suitable for high reference fast setting PLLs. Proposed PFD consumes 324 W power from 1.2V supply at maximum operating frequency. It oc- cupies an active area of 322.612 m2. Lock acquisition process is tested with 1 GHz prototype PLL. Charge pump circuits used in many wide bandwidth PLL designs demand operational ampli ers for reducing the mismatch currents which make the circuits power hungry. In this work, a low mismatch charge pump cir- cuit is proposed which uses a novel mismatch compensation technique for reducing the mismatch in charging and discharging currents of the loop lter without having any extra area and power overhead. Proposed cir- cuit is designed for 100 A charge pump current (ICP ) and it achieves less than 1% mismatch current across all process corners for an output volt- age compliance range of 0.2 to 1 V. A prototype circuit of 1 GHz PLL is designed in 65nm CMOS technology for testing the proposed charge pump. It achieves -81.2 dBc spur-level at reference frequency of 250 MHz. In locked condition of the PLL, proposed charge pump consumes 176 W power from 1.2V supply including the reference current. Area occupied by the proposed design is 2520 m2. Finally, high speed inductor-less PLL is implemented in UMC 65nm CMOS

technology for a wide frequency range from 1.25 to 5 GHz. This circuit is implemented with two stage cascaded charge pump PLL architecture. In this design, proposed circuits of PFD, charge pump and VCOs are used. Two VCOs are designed for this PLL implementation. First stage VCO is a simple 3-stage ring oscillator of 625 MHz. A feed-forward coupled 8- phase programmable VCO for frequency range of 1.25 to 5 GHz is designed for the second stage. First stage VCO o ers PVT compensated 625MHz frequency achieving -114 dBc/Hz phase noise at 1 MHz o set frequency. This cascaded PLL exhibits 1.44 ps rms jitter at 5 GHz output frequency using a reference frequency of 25 MHz. It acheives jitter FOM and jitter-N FOM of -227.1 and -250.1 dB, respectively. This complete cascaded PLL occupies an active area of 0.079mm2 and consumes 9.24mW power from 1.2V supply at 5 GHz output frequency.