Hardware Co-simulation of Pulse Amplitude Modulation Controlled BLDC Motor

Abstract

This paper describes the validation of a Field Programmable Gate Array (FPGA)-based controller for Brushless Direct Current (BLDC) motor drive using the hardware co-simulation feature enabled in the Xilinx System Generator (XSG) design tool. To control the speed of the BLDC motor, the proposed BLDC drive uses PAM control of the Voltage Source Inverter (VSI). The PAM control reduces switching losses by allowing the VSI to operate at the frequency determined by synchronous speed. At the front end, a bridgeless SEPIC provides a wide range of DC voltage to the VSI input. When compared to the topology with two separate inductors, the Bridgeless SEPIC coupled inductors reduce the overall component count and the self-inductance required. The converter is designed to operate in Discontinuous Conduction Mode (DCM) by applying a simple voltage follower approach to a SEPIC converter to achieve inherent input current shaping over a wide speed range. The precise reference voltage for the DC link is calculated in the outer speed control loop. The proposed BLDC motor drive is modeled using the XSG design tool, and the controller is implemented in FPGA. Hardware co-simulation is used to evaluate the controller's performance under dynamic conditions such as step changes in reference speed and supply voltage. © 2022 IEEE.