Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks

Abstract

The networks-on-chip (NoCs) as the prevalent interconnection infrastructure have been continuously replacing the contemporary chip microprocessors (CMPs) while high performance computing is the dominant consideration. Aggressive technology scaling progressively reduces the feature size of the chips resulting in increasing susceptibility to failures and breakdowns due to open faults on communication channels. The reliability and performance issues are then becoming more critical requirement in both current and future NoC-based CMPs. This paper first presents an on-line, distributed built-in-self-test (BIST) oriented test mechanism that particularly detects open faults on communication channels and identifies faulty wires from the channels in NoCs. Next, a suitable test scheduling scheme is presented in order to reduce the overall test time and related performance overhead due the fault. Such scheduling scheme makes the present test solution scalable with large scale NoC architectures in general. Implementation of the test mechanism takes little hardware area and few clocks to detect the fault in channels. The on-line evaluation of the proposed test solution demonstrates the effect of the channel-open faults on the NoC performance characteristics at large real like synthetic traffic. In comparison to wide range of prior works on 16-bit networks, the present scheme provides many advantages, e.g., it improves hardware area overhead by 35.36–67.73% and saves the test time by 96.43%. packet latency and energy consumption by 5.83–42.79% and 6.24–46.38%, respectively on the networks, the proposed scheme becomes competitive with the existing works. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.