History aware interference distance based Page replacement policy for Hybrid Memory

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dc.contributor.authorRai, S.
dc.contributor.authorTalawar, B.
dc.date.accessioned2026-02-06T06:34:21Z
dc.date.issued2024
dc.description.abstractHybrid memories comprising of DRAM-NVM or DRAM-CXL based devices are emerging as potential alternatives to overcome the drawbacks of monolithic DRAM based memories. This arrangement in the memory hierarchy will bring a paradigm shift and there is a necessity to re-look the existing policies. This work proposes an ideal page replacement policy for hybrid memories. © 2024 IEEE
dc.identifier.citationProceedings of the IEEE International Conference on High Performance Computing, Data, and Analytics Workshops, HiPCW, 2024, Vol., 2024, p. 219-220
dc.identifier.issn27700151
dc.identifier.urihttps://doi.org/10.1109/HiPCW63042.2024.00087
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/29202
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.subjectHybrid Memories
dc.subjectInter-reference distance
dc.subjectNon-volatile Memories
dc.titleHistory aware interference distance based Page replacement policy for Hybrid Memory

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