Design of Arithmetic Logic Unit Using Energy Charge Recovery Adiabatic Logic Technique

Abstract

In arithmetic logic units (ALUs), one-bit full adder cells are the most widely used digital circuit elements. Arithmetic operations are performed using Full-Adder (FA). They are also the core functionality of all computational circuits. Arithmetic and logic operations are performed by an arithmetic-logic unit, which is a component of a central processing unit. In this article, the objective is to lower the power consumption and increase design performance using adiabatic logic technique. For this, FA, Multiplxer, and ALU are designed using adiabatic logic are implemented and simulated in Mentor Graphics at 180nm technology. The results prove a total consumed power of 90.719 pW at supply of 1.8 V for FA and ALU has a total power consumption of 3.693nW and PDP 182.1∗10-19. © 2024 IEEE.