Exploration of SOT-MRAM based Devices in Memory Hierarchy for Next-Generation Computing

Abstract

The “MemoryWall” problem, whichrefers to the increasing gap between CPU pro cessing speed and memory access time, is a significant challenge in modern computing systems. Traditional Static Random Access Memory (SRAM) caches have limitations such as high area, leakage power and scalability issues, especially as Complementary Metal-Oxide-Semiconductor (CMOS) technology scales. This necessitates exploring alternative memory technologies. Spin-Orbit-Torque Magnetic RAM (SOT-MRAM) stands out due to its separate read and write paths, lower leakage power, and higher endurance than Spin-Transfer Torque Magnetic RAM (STT-MRAM) and other non-volatile memory technologies. The first part of the thesis work proposes a Multi-Factor Scaling (MFS) framework for utilizing SOT-MRAM as an alternative to SRAM caches to address the absence of a scaling road map and structural influence of memory cells. The focus is on applications such as Artificial Intelligence (AI), Natural Language Processing (NLP), and general purpose workloads. This work introduces an advanced MFS framework for evaluating the impact of SOT-MRAM density replacement in cache memory design for power performance improvement. The framework includes Design Space Exploration (DSE) across various scaling scenarios, comparing SRAM and SOT-MRAM configurations. Second, the work proposes and investigates the achievable Relative Lifetime Im provement (RLI) through the use of a Physical Split Cache (PSC) with Virtual Re ordering (VRO), which dynamically manages Write Variation (WVAR) to extend cache lifetime and reliability. The PSC design leverages the advantages of both technologies: the high-speed access of SRAM and the energy efficiency and non-volatility of SOT MRAM. The VRO algorithm optimizes cache performance by dynamically reordering cache lines to balance write distribution and enhance endurance. Finally, this research work explores the integration of SOT-MRAM as an alterna tive to DRAM in main memory systems, targeting embedded systems and multi-core environments. The lack of publicly available parameters for SOT-MRAM poses a challenge in evaluating its performance with reliable simulations. Therefore, micro architectural DSE and comprehensive full-system simulations are employed to derive and validate the necessary parameters for robust analysis of SOT-MRAM-based mem ory systems under various configurations and capacities. The research methodology involves evaluating benchmark programs representing diverse application domains to assess the performance, energy efficiency, and relia bility of SOT-MRAM compared to traditional memory technologies. The findings show that SOT-MRAM significantly improves power efficiency, reduces latency, and enhances overall system performance, making it a compelling alternative for modern computing systems. In summary, this thesis presents an end-to-end framework for rapidly evaluating and adopting SOT-MRAM in cache and main memory designs. The comprehensive analysis and simulation results emphasize SOT-MRAM’s poten tial to overcome the limitations of SRAM and DRAM, providing scalable and efficient memory solutions for advanced applications. The insights gained from this research lay the groundwork for future developments in the memory hierarchy, ensuring that com puting systems can meet the increasing demands of AI, NLP, and other data-intensive workloads.