Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection Networks

Abstract

With the rapid developments in VLSI technology, the communication channels in networks-on-chip (NoCs) can place many wires for sustaining high-performance requirements over the communication bottleneck in multicore, multiprocessor systems-on-chip (MPSoCs). Consequently, NoC channels, due to increased wire density, are exposed to different logic level faults, e.g., short resulting in reliability and yield issues in NoC-based systems. These faults can appear at any stage of the lifetime of a chip. While existing in an NoC communication architecture, the channel-short faults bring the system into various failures that surprisingly cause a significant deviation from its expected performance. In this work, an online, distributed test solution is presented that detects and diagnoses intra-channel and inter-channel short faults and analyzes the effect of these faults on various performance metrics. Fault simulations ensure up to 100% coverage metrics. Network simulation shows insight into the impact of channel shorts in NoC performances. It is observed that the amount of test time is reduced to 10 × concerning a set of prior works while employed for a group of NoCs. It is also seen on these NoCs that average packet latency is improved by 15.14–46.79% while energy consumption is reduced by 13.68–39.13% by the current solution than the set of existing solutions. Moreover, the proposed solution scales to all NoCs irrespective of size, topology, and channel width at an acceptable test cost. © 2023, The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd.