High Speed and Low Power DSP Architectures for Barker-13 Radar Pulse Compressor

Abstract

This paper proposes two novel efficient DSP architectures for the Barker-13 sequence for radar coded waveform design. Firstly, the traditional pulse compressor architectures are modified by using unfolded DSP techniques to achieve higher sampling rates for high-speed applications. Secondly, the reduction in hardware utilization and power consumption are addressed by the folding technique. Further, the proposed architectures are implemented on Artex-7 Field Programmable Gate Arrays (FPGA). The hardware implementation results demonstrates that the unfolded pulse compressor increased the speed by 3.25 times compared to traditional broadcasting filter realization. On the other hand, the folded architecture reduced the power usage by 15.2% in comparison to broadcast architecture. These pulse compressors can be deployed for high speed and low power radar/sonar applications. © 2022 IEEE.