Design and modelling an attack on multiplexer based physical unclonable function

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dc.contributor.authorVenkata, A.M.
dc.contributor.authorJeeru, D.R.
dc.contributor.authorVittal, K.P.
dc.date.accessioned2026-02-05T09:28:28Z
dc.date.issued2020
dc.description.abstractThis paper deals with study of the physical unclonable functions and specifically the design of arbiter based PUF (APUF) and extends the work on different types of attacks on the PUF designs to break the security of the device, which includes advanced computational algorithms. Machine learning (ML) based attacks are successful in attacking existing designs. So in this, the resistance of the modified, proposed design of APUF is examined by modelling the attack based on the logistic regression a MLbased algorithm. The design is validated on Basys-3 Artix -7 FPGA board with a part number (xc7a35tcpg236-1). © 2020 Seventh Sense Research Group. All rights reserved.
dc.identifier.citationInternational Journal of Engineering Trends and Technology, 2020, 68, 6, pp. 63-67
dc.identifier.issn23490918
dc.identifier.urihttps://doi.org/10.14445/22315381/IJETT-V68I6P210S
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/23859
dc.publisherSeventh Sense Research Group
dc.subjectFPGA
dc.subjectHardware security
dc.subjectLogistic regression
dc.subjectMachine learning
dc.subjectPUF
dc.subjectVerilog
dc.titleDesign and modelling an attack on multiplexer based physical unclonable function

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