Nanoscale Tapered Hybrid Plasmonic Waveguide for On-Chip Silicon Photonics

Abstract

Plasmonic waveguides which deploy surface plasmon-polariton (SPP) waves are of colossal interest to the researchers with their ability to realize and integrate nanophotonic circuits beyond the diffraction limit. In order to subjugate the demerits of plasmonic and dielectric waveguides, the light guided by plasmonic and dielectric waveguides are coupled to form hybrid plasmonic waveguide (HPWG). In this work, we have simulated a nanoscale tapered plasmonic waveguide (Au-SiO<inf>2</inf>-Si) using COMSOL Multiphysics software in the telecommunication C-band. The proposed waveguide shows better normalized effective mode area (A<inf>e</inf><inf>f</inf><inf>f</inf>/A= 0.056), enhanced electric field confinement, and long propagation length (L<inf>p</inf> = 101.55 μm) with h= 350 nm, W<inf>Au</inf> = 100 nm, W<inf>Slot</inf>=20 nm, W<inf>Si</inf> = 220 nm, and h<inf>t</inf>=150 nm. The finite element method based approach shows that this enounced waveguide is a feasible choice for the future on-chip nanophotonic devices. © 2021, Springer Nature B.V.