TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCs

Abstract

With the increasing computational requirements of complex Systems on Chips (SoCs), the number of Universal Serial Interface (USI) instances have been scaled up, for handling data from ever greater number of peripheral components. This has increased the testbench (TB) complexity during verification, requiring numerous test vectors across multiple iterations to validate the design logic, negatively affecting turn-around-time. In this paper, we propose the TestQuBE (Testbench Quality Benchmark Enhancement) methodology which targets four TB quality benchmarking metrics: total TB development time, resource utilization, functional coverage development efficiency. TestQuBE generates an enhanced testbench with automated components that target the aforementioned TB quality metrics. Simulation results for a real-time use-case scenario show 76.2% improvement in functional coverage for up to 75% faster TB development time, resulting in a 91.6% reduction in resource utilization and approximately 50x greater development efficiency, compared to deployed solutions. © 2021 IEEE.