This paper presents a design & implementation methodology for FPGA based MIL-STD-1553 Remote Terminal Sub-System using DDC's BU-61580 device. The interesting part of this paper is that it presents a design of non-processor remote terminal sub-system. The glue logic is put on one FPGA of 176 pins which initializes the BU-61580 in RT mode at power-on. The FPGA design was done using Viewlogic & Actel packages. The simulation has shown the correct results which was then followed by the implementation. In this paper, the design is presented for 9 sensors among which 5 are analog and 4 are digital. For the purpose of testing the circuit, the analog & digital sensors are simulated through the computer.
| dc.contributor.author | Bhagyalakshmi, K. | |
| dc.contributor.author | Ramachandra, G. | |
| dc.contributor.author | Agrawal, V.K. | |
| dc.contributor.author | Subbanna Bhat, P. | |
| dc.contributor.author | Philar, S.R. | |
| dc.date.accessioned | 2026-02-05T11:00:32Z | |
| dc.date.issued | Design and implementation of FPGA based non-processor MIL-STD-1553 remote terminal sub-system using DDC's BU-61580 | |
| dc.description.abstract | 1999 | |
| dc.identifier.citation | Journal of Spacecraft Technology, 1999, 9, 2, pp. 21-32 | |
| dc.identifier.issn | 9711600 | |
| dc.identifier.uri | https://idr.nitk.ac.in/handle/123456789/28029 | |
| dc.publisher | ISRO Satellite Centre | |
| dc.subject | Computer simulation | |
| dc.subject | Error correction | |
| dc.subject | Field programmable gate arrays | |
| dc.subject | Remote control | |
| dc.subject | Sensor data fusion | |
| dc.subject | Non-processor remote terminal sub-systems | |
| dc.subject | Communication satellites | |
| dc.title | This paper presents a design & implementation methodology for FPGA based MIL-STD-1553 Remote Terminal Sub-System using DDC's BU-61580 device. The interesting part of this paper is that it presents a design of non-processor remote terminal sub-system. The glue logic is put on one FPGA of 176 pins which initializes the BU-61580 in RT mode at power-on. The FPGA design was done using Viewlogic & Actel packages. The simulation has shown the correct results which was then followed by the implementation. In this paper, the design is presented for 9 sensors among which 5 are analog and 4 are digital. For the purpose of testing the circuit, the analog & digital sensors are simulated through the computer. |
