Analytical insights into threshold voltage behaviour of vertical linearly doped fully depleted silicon-on-insulator MOSFETs

Abstract

This paper presents a novel two-dimensional (2D) analytical model for the surface potential of a vertical linearly doped (VLD) fully depleted silicon-on-insulator (FDSOI) FET. Moreover, the channel electric field and threshold roll-off are modeled using the surface potential equations. The evanescent-mode analysis method has been employed to determine the channel potential, and ATLAS TCAD is utilised to simulate the subthreshold I–V characteristics of the device. The performance of the proposed device has been compared with the calibrated FDSOI FET. The proposed device demonstrates remarkable improvements over conventional FDSOI FETs: off-state leakage current plunges from 100 nA to 12 pA, while subthreshold swing sharpens from 110 mV dec?1 to 85 mV dec?1, yielding an exceptional ON-to-OFF current ratio enhancement from 7.2 × 103 to 2.8 × 107. The linearly doped channel in the proposed device is developed using the hetero epitaxy method. The proposed device can be used in integrated circuits (ICs) for low-power applications such as laptops and mobile phones. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.