Faculty Publications

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Publications by NITK Faculty

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Subject: search.filters.subject.Post layout simulation

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    Low power ultra wide-band balun LNA using noise cancellation and current-reuse techniques
    (Elsevier Ltd, 2017) Vasudeva Reddy, K.; Girija Sravani, K.; Prashantha Kumar, P.
    A low power, single to differential (balun) low noise amplifier (LNA) using noise cancellation and current re-use techniques is presented for ultra wide-band applications. An upsurge balun LNA is designed using UMC 0.18-?m RF CMOS technology with an emphasis on the covenant between gain, bandwidth and power dissipation. The proposed balun exerts a differential stage on top of common gate-common source (CG-CS) stage. A CG-CS stage exploits amalgamation of CG stage (for wide-band impedance matching) and CS to curtail gain and phase imbalance, while simultaneously negating the noise and distortion of input matching transistor. The escalation of bandwidth has been accomplished using staggered tuning on CG-CS and differential stages. The stacked differential amplifier does cancellation of self noise as well as supply noise. The proposed UWB balun LNA achieves 14 dB voltage gain with agreeable input reverse isolation (S11) of <-8dB over the frequency range of 3.19–8.8 GHz. The minimum noise figure of 3.9 dB and P1dB of ?10.5 dBm while exhausting 3.8 mW from 1.2 V supply. The superlative performance of balun LNA is accomplished between 3.19 and 8.8 GHz with gain and phase errors below 0.2 dB and 0.40 respectively. The layout occupying 0.77 mm2 area. The overall pre and post layout simulations of proposed LNA shows admissible agreement with theoretical predictions. © 2017 Elsevier Ltd
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    PVT compensated high selectivity low-power balun LNA for MedRadio communication
    (Institution of Engineering and Technology journals@theiet.org, 2018) Vasudeva Reddy, V.R.; Herolli, P.K.; Shojaei Baghini, M.S.
    A single-to-differential low-noise amplifier (LNA) is proposed for low-power medical devices in the frequency band of 401-406 MHz. The proposed LNA avoids the use of surface acoustic wave (SAW) filter and additional balun in RF receiver front-end. The LNA comprises inductive degeneration common source (IDCS) technique (stage I) and a cascaded common source circuit (stage II). The stage-II is stacked on top of stage-I. The proposed balun LNA incorporates single to differential (SD) conversion for minimum gain and phase error. A compensation bias circuit is proposed to minimise variations in parameters of LNA against process corners, supply voltage and temperature (PVT). An upsurge balun LNA is designed in UMC 0.18-?m CMOS technology, the DC power consumption is 290 ?W under a supply voltage of 1 V and the minimum noise figure is 3 dB. The die area of LNA including buffers and bias circuit is 850 ?m × 978 ?m. The worst-case post layout simulation results show a gain and phase error of 0.8 dB and 10°. The percentage variation of gain and NF against PVT is reduced by 55 and 48%. Furthermore, the balun LNA has out of band rejection at the roll-off rate better than 70 dB/dec. © 2018, The Institution of Engineering and Technology.
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    A 0.3?V, 56?dB DR, 100?Hz fourth order low-pass filter for ECG acquisition system
    (Elsevier Ltd, 2019) Polineni, S.; Hanumantha Rao, G.; Rekha, S.; Bhat, M.S.
    This paper proposes an extremely low voltage, low power bulk-driven voltage follower (BD-VF). As an application of the proposed BD-VF, a 4th order low-pass filter (LPF) with cutoff frequency adjustable from 50 Hz to 250 Hz is designed for electrocardiogram (ECG) acquisition systems. The filter is implemented in UMC 180 nm CMOS technology occupying only 0.03 mm2 area. Post layout simulation results show that the filter offers 56 dB dynamic range even with an extremely low supply voltage of 0.3 V. The total power consumption of the filter is 4.8 nW for a cutoff frequency of 100 Hz. The Figure-of-merit (FoM) and capacitance/pole of the filter are 5.7 × 10?15 and 2.2 pF respectively. The proposed filter offers the lowest FoM compared to the state-of-the-art nW-class filters. © 2019 Elsevier Ltd
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    A 0.3-V, 2.4-nW, and 100-Hz fourth-order LPF for ECG signal processing
    (John Wiley and Sons Ltd cs-journals@wiley.co.uk, 2020) Rao G, H.; Polineni, P.; Rekha, S.; Bhat, M.S.
    An ultra-low voltage, low power bulk-driven voltage follower (VF) is proposed in this paper. Further, it is exploited to design a fourth-order low-pass filter (LPF) for electrocardiogram (ECG) signal processing. The filter is designed in UMC 180-nm CMOS technology and operates with an ultra-low supply voltage of 0.3 V. It consumes an extremely low power of 2.4 nW for a cutoff frequency of 100 Hz. Results of post-layout simulation show that the proposed filter provides a dynamic range (DR) of 51.6 dB even from a 0.3-V supply voltage. The filter achieves a Figure-of-merit (FoM) of 4.7 × 10?15, which is better than many designs listed in the literature. © 2020 John Wiley & Sons, Ltd.
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    A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications
    (John Wiley and Sons Inc, 2021) Polineni, S.; Rekha, S.; Bhat, M.S.
    A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 ?W across target resolutions (8–15 bits). © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.