Faculty Publications
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Publications by NITK Faculty
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Item A 0.5V 300μW 50MS/s 180nm 6bit Flash ADC using inverter based comparators(2012) Komar, R.; Bhat, S.M.; Laxminidhi, T.This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 300 μW. © 2012 Pillay Engineering College.Item A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC(2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, S.M.This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. © 2012 IEEE.Item Switched inverter comparator based 0.5 v low power 6 bit Flash ADC(2012) Komar, R.; Bhat, S.M.; Laxminidhi, T.This paper presents an ultra low power 6 bit Flash ADC designed in 180 nm CMOS technology for ultra low power applications. The design uses inverter based comparators to reduce the silicon area and power requirement. A novel clock delaying technique is used to power on the three stages of the comparator which work in series. This reduces the power consumption and increases speed of operation. Fat tree architecture is used to design the digital encoder. The power supply used for the design is 0.5 V and the sampling rate is 50 MS/s. The design consumes ultra low power of 600 μW and spans a very small area of 0.164 mm2. In literature this is found to be the lowest for 6 bit ADCs in 180 nm with sampling frequency of 5 MS/s or above. The SNDR remains above 31.5 dB in the whole input frequency range of 0 to 25 MHz. The ADC has maximum DNL of 0.85 LSB and maximum INL of 1 LSB. The FOM of the ADC is found to be 0.39 pJ/conv. © 2012 IEEE.Item A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption(2013) Lad, K.; Bhat, M.S.A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. © 2013 IEEE.Item An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC(Institute of Electrical and Electronics Engineers Inc., 2016) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.This paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 μW from the power supply of 1V. © 2015 IEEE.Item Single inductor dual output buck converter for low power applications and its stability analysis(IEEE Computer Society help@computer.org, 2018) Sankaranarayanan, S.; Vinod, K.C.; Sreekumar, A.; Laxminidhi, L.; Singhal, V.; Chauhan, R.The applications like sensor nodes and wearables, which run on coin/button cell and/or harvested energy source need small form factor and very low power consumption. A single inductor multiple output (SIMO) converter provides saving on inductor count and hence becomes a right choice for such applications. This paper presents a single inductor dual output (SIDO) buck converter targeting light load applications. The architecture uses discontinuous conduction mode (DCM) with pulse frequency modulation (PFM) control and the switching scheme ensures almost zero cross-regulation. The proposed converter is simulated in 180 nm CMOS technology showing zero cross-regulation. An efficiency of above 88% is achieved considering inductor and package losses in load range of micro-Amperes to a few milli-Amperes. This paper also presents a detailed stability analysis and model for the selected SIMO architecture along with some interesting observations and inferences derived from this analysis. © 2018 IEEE.Item A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture(IEEE Computer Society help@computer.org, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact switched capacitor integrator (SCI) based successive approximation register (SAR) analog to digital converter (ADC) for data acquisition system is presented. This technique requires an operational transconductor amplifier (OTA), a comparator and four equal sized capacitors of moderate value for fully differential approach and the architecture is resolution independent. The reference voltage is generated by charge sharing between a reference capacitor and the input capacitor of a switched capacitor (SC) integrator. The DAC voltage for comparison is generated by accumulating the charges on the SC integrating capacitor. ADC being fully differential nature has wide input range and it is parasitic insensitive to a large extent. As a stand alone data converter it has small capacitance spread and hence its input capacitance is easy to drive. A 10 bit 0.9MHz sampling rate SAR ADC is designed using 180 nm CMOS technology, operating at 1.8 V supply, has effective number of bits (ENOB) of 9.5 at Nyquist frequency. The ADC occupies small die area compared to SAR with a binary weighted capacitor array. © 2019 IEEE.