Faculty Publications
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Item Modeling and design of field programmable gate array based real time robust controller for active control of vibrating smart system(Academic Press, 2015) Parameswaran, A.P.; Ananthakrishnan, B.; Gangadharan, K.V.The current paper focuses on accurate mathematical modeling of a vibrating piezoelectric laminate cantilever beam theoretically as well as experimentally so as to obtain the best replication of the system dynamics on the software platform for simulation studies. The developed models were tested for accuracy in time as well as frequency domain by employing the sweep sine test. The focus of the study is on the flexural modes of vibrations of the cantilever beam. Here, modeling is focused on the first vibratory mode as it has been observed that the effects of felt vibrations would be maximum in terms of system stability and its operational efficiency when the excitation frequency matches with the first natural frequency of the system (fn1). This was validated by appropriate non-parametric modeling of the smart system by subjecting it to the Impact Hammer test. Development of accurate system models play an important role in designing and testing various control algorithms for reliable active vibration control (AVC). In the final stage, a real time active vibration robust controller was designed using a proportional derivative sliding mode control (PDSMC) technique and deployed on a Field Programmable Gate Array (FPGA) platform. The efficiency of the developed real time controller was proved in time as well as frequency domains by subjecting the closed loop system to harmonic excitations at first natural frequency as well as sweep sine test focussing on the first vibratory mode with the conclusion that the developed controller will function satisfactorily at higher modes of vibrations. © 2015 Elsevier Ltd.Item Design and development of a model free robust controller for active control of dominant flexural modes of vibrations in a smart system(Academic Press, 2015) Parameswaran, A.P.; Ananthakrishnan, B.; Gangadharan, K.V.Real physical vibrating smart systems exhibit a lot of nonlinearities in their dynamics. Undesirable vibrations, particularly in the regions of first as well as second resonance, play a very important role in deteriorating the stability of the system as well as its operational efficiency. The work presented in the paper focuses on an analytical technique of mathematical modeling of a vibrating piezoelectric laminate cantilever beam which is considered to be the smart system. The natural frequencies of the vibrating smart system are determined from the ANSYS simulation studies and experimentally, it is found that the vibrations induced voltage is maximum at the first followed by the second natural frequencies. Hence, the smart system is modeled analytically through finite element technique using the Euler-Bernoulli beam theory for the first two flexural modes of vibrations. To account for the possible nonlinearities, a suitable robust controller is designed based on sliding mode technique. Simulation studies on the developed analytical model indicated a high performance of the designed controller in controlling the vibrations at first and second resonance regions. Also, the designed controller was found to be effective in its operations when the excitation varied over a large range covering the first two natural frequencies. In the final stage, the designed robust controller was successfully prototyped on a Field Programmable Gate Array (FPGA) platform using LabVIEW coupled with Compact Reconfigurable Input Output (cRIO-9022) controller configured in its FPGA interface mode and the resulting robust FPGA controller successfully controlled the occurring system vibrations. © 2015 Elsevier Ltd.Item Investigation of CMOS Based Integration Approach Using DAI Technique for Next Generation Wireless Networks(Springer New York LLC barbara.b.bertram@gsk.com, 2019) Roy, G.M.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.This research work investigates a CMOS based low noise amplifier (LNA) using differential active inductor with eight-shaped patch antenna for next generation wireless communication. The proposed work conceded into three different phases. The first phase proposes LNA architecture which includes multistage cascode amplifier with a gate inductor gain peaking technique. The ground approach for this architecture employs active inductor technique that includes two stages of differential amplifier. The proposed novel technique leads to give incremental in inductance by using of common mode feedback resistor and lowers the undesirable parasitic resistance effect. Additionally, this technique offers gain enhanced noise cancellation and achieves a frequency band of around 5.7 GHz. The proposed architecture includes single stage differential AI and enhances the bandwidth up to 6.8 GHz with peak gain of 21 dB at 7.8 GHz. The noise figure and stability factor are achieved which is reasonably good at 1 dB. The proposed architecture is design and optimized on advanced design RF simulator using 0.045 µm CMOS process technology. While in second phase, a narrow band eight-shaped patch antenna is designed which provides operating band range from 5.8 to 6.5 GHz with 6.2 GHz resonating frequency. Highest peak gain of 15 dB and maximum radiation power of 42.5 dBm is succeed by proposed antenna. The final phase provides integration strategy of LNA with antenna and achieves desired gain of nearly 21 dB with minimum NF of 1.2–1.5 dB in the same band. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.Item YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAS(World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2019) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the 6×6 mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the 6×6 mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively. © 2019 World Scientific Publishing Company.Item LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA(Association for Computing Machinery acmhelp@acm.org, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.An FPGA-based Network-on-Chip (NoC) using a low-latency router with a look-ahead bypass (LBNoC) is discussed in this article. The proposed design targets the optimized area with improved network performance. The techniques such as single-cycle router bypass, adaptive routing module, parallel Virtual Channel (VC), and Switch allocation, combined virtual cut through and wormhole switching, have been employed in the design of the LBNoC router. The LBNoC router is parameterizable with the network topology, traffic patterns, routing algorithms, buffer depth, buffer width, number of VCs, and I/O ports being configurable. A table-based routing algorithm has been employed to support the design of custom topologies. The input buffer modules of NoC router have been mapped on the FPGA Block RAM hard blocks to utilize resources efficiently. The LBNoC architecture consumes 4.5% and 27.1% fewer hardware resources than the ProNoC and CONNECT NoC architectures. The average packet latency of the LBNoC NoC architecture is 30% and 15% lower than the CONNECT and ProNoC architectures. The LBNoC architecture is 1.15× and 1.18× faster than the ProNoC and CONNECT NoC frameworks. © 2020 Association for Computing Machinery.Item P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA(Springer, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall performance of CMPs and MPSoCs significantly. We propose P-NoC: an FPGA-based parameterized framework for analyzing the performance of NoC architectures based on various design decision parameters in this paper. The mesh and a multi-local port mesh (ML-mesh) topologies have been considered for the study. By fine-tuning various NoC parameters and synthesizing on the FPGA, identify that the performance of NoC architectures are influenced by the configuration of router parameters and the interconnect. Experiments show that the flit width, buffer depth, virtual channels parameters have a significant impact on the FPGA resources. We analyze the performance of the NoCs on six traffic patterns viz., uniform, bit shuffle, random permutation, transpose, bit complement and nearest neighbor. Configuring the router and the interconnect parameters, the ML-mesh topology yields 75% lesser utilization of FPGA resources compared to the mesh. The ML-mesh topology shows an improvement of 33.2% in network latency under localized traffic pattern. The mesh and ML-mesh topologies have 0.53× and 0.1× higher saturation throughput under nearest neighbor traffic compared to uniform random traffic. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item Backstepping Controller with Dual Self-Tuning Filter for Single-Phase Shunt Active Power Filters under Distorted Grid Voltage Condition(Institute of Electrical and Electronics Engineers Inc., 2020) Jayasankar, V.N.; Vinatha Urundady, U.This article presents the design and hardware implementation of an adaptive nonlinear controller for fast, robust, and stable control of single-phase shunt active power filter. The proposed control system consists of two control loops: an inner harmonic current compensation loop and an outer dc-voltage control loop. The inner loop is realized using self tuning filter based instantaneous power theory (pq theory). The limitations of conventional low-pass filter based fundamental component extraction methods are overcome using self-tuning filter. The outer loop is realized backstepping controller (BSC). The limitations observed in existing dc-link voltage controllers like poor stability margin, steady state error, chattering problem, etc., are overcome by the proposed BSC. The switching loss estimation is introduced in BSC using design estimation rules to enhance the dc-link loss compensation capability. The stability of the system with the proposed controller is studied using Barbalat lemma. A laboratory prototype of BSC based shunt active power filter is implemented. The control algorithm is implemented in a single all on chip field programmable gate array (FPGA). To ensure the effectiveness of the controller in mitigating the harmonic currents and controlling dc-link voltage, the control algorithm is tested under steady state and dynamic conditions. © 1972-2012 IEEE.Item Active feedback supported CMOS LNA blended with coplanar waveguide-fed antenna for Wi-Fi networks(John Wiley and Sons Inc, 2021) Roy, G.M.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi-Fi networks. The LNA design-I, involves a cascode amplifier followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor-less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design-II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign-III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost. © 2021 The Authors. IET Microwaves, Antennas & Propagation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.Item A Mixed Parallel and Pipelined Efficient Architecture for Intra Prediction Scheme in HEVC(Taylor and Francis Ltd., 2022) Poola, L.; Aparna., P.The complexity of intra prediction in High-Efficiency Video Coding (HEVC) is increased significantly due to the incorporation of inherent features like variable-sized quadtree partitioned coding units and 35 angular modes that help in achieving better compression. This paper presents an efficient hardware architecture for the intra prediction that supports and comprises the above aspects and achieves a higher throughput to support high definition (HD) videos. A compact reusable reference buffer structure is implemented to limit the buffer size to 1 KB. A dedicated arithmetic unit to take advantage of the parallelism present in the prediction algorithm is incorporated, which allows the reuse of multipliers to reduce hardware resources. The loading of reference samples to buffers for prediction causes significant delays which are eliminated in our design. The entire architecture functions as a pipelined unit with no data dependency and generates eight samples/clock cycle in parallel. The design is implemented on a Field Programmable Gate Array (FPGA) platform operating at a frequency of 110 MHz. This makes it possible to support 4 K videos at 30 frames per second, with the resource cost of 16 K logic gates and 122 registers. © 2022 IETE.Item LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures(World Scientific, 2022) Kumar, A.; Talawar, B.Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from 2×2 to 45×45 are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is 5000× to 5500× with respect to BookSim simulator. © 2022 World Scientific Publishing Company.
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