Faculty Publications
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Item Widely programmable high-frequency active RC filters in CMOS technology(Institute of Electrical and Electronics Engineers Inc., 2009) Laxminidhi, T.; Prasadu, V.; Pavan, S.We propose a circuit technique that enables the realization of widely programmable high-frequency active RC filters in CMOS technology. A fifth-order Chebyshev ladder filter having a digitally programmable 3-dB bandwidth (from 44 to 300 MHz) is used as a vehicle to validate our ideas. The opamp uses feedforward compensation for achieving high dc gain and wide bandwidth. The integrating resistors are realized as a series combination of a triode-operated MOSFET and a fixed polysilicon resistor. A charge-pump-based servo loop servoes the integrating resistor to a stable off-chip resistor. The principle of "constant capacitance scaling"is applied to the opamp and the integrating resistors so that the shape of the frequency response is maintained when the bandwidth is scaled over a 7 7times; range. The filter core, designed in a 0.18-?m CMOS process, consumes 54 mW from 1.8-V supply and has a dynamic range of 56.6 dB. © 2009 IEEE.Item Effect of boiling surface vibration on heat transfer(Springer Verlag service@springer.de, 2017) Sathyabhama, A.Experimental investigation of effect of forced vertical surface vibration on nucleate pool boiling heat transfer of saturated water at atmospheric pressure is presented in this paper. Vertical vibration was induced externally to the circular copper test surface on which boiling took place, using a vibration exciter. Frequency was varied in the range 0–25 Hz and amplitude of vibration was varied in the range 0–5 mm. Boiling takes place at much lower superheats for the same heat flux, slope of boiling curve decreases remarkably, when the surface is given external excitation. High frequency and high amplitude oscillations lead to more intensive heat transfer. There are some combinations of frequency and vibration amplitude, which cause up to two times increase in heat transfer coefficients. © 2016, Springer-Verlag Berlin Heidelberg.Item Analysis and Design of a High-Frequency Isolated Full-Bridge ZVT CLL Resonant DC-DC Converter(Institute of Electrical and Electronics Engineers Inc., 2019) Patil, U.; Nagendrappa, N.In this paper, a new pulsewidth modulated gating scheme and a zero-voltage transition (ZVT) auxiliary circuit is proposed for a fixed frequency full-bridge CLL dc-dc resonant converter with a capacitive output filter. An approximate complex ac circuit approach is used for the steady-state analysis of the converter. The optimum design of the converter is described with the help of design curves for a sample converter of 200-W power rating operating at a switching frequency of 100 kHz. The converter with applied gating scheme and ZVT auxiliary circuit provides zero-voltage switching to all the switches for the entire variations in loading and input voltage conditions ensuring higher conversion efficiency. PSIM simulations are carried out to verify theoretical predictions about the performance of the converter for various operating conditions. Finally, experimental results are provided to verify the feasibility of the proposed converter. The theoretical, simulation, and experimental results are given and discussed. © 1972-2012 IEEE.Item Performance evaluation of high-frequency CLL resonant DC–DC converter operated with phase-shift and modified PWM gating scheme: Analysis, design and implementation(Institution of Engineering and Technology, 2020) Patil, U.; Nagendrappa, N.Normal phase-shift and modified pulse-width modulation gating schemes are proposed for a full bridge high-frequency capacitor–inductor–inductor (CLL) resonant DC–DC converter, and its performance is analysed in this study. Detailed modelling and the steady-state analysis of the converter are performed by using the fundamental harmonic approximation approach. Various modes of the converter operation with both the gating schemes are described and examined in detail. Zero-voltage switching of all the main switches is achieved by designing the resonant converter to operate in the above resonance mode. The optimum design of the converter is illustrated with the help of a flowchart and design curves. PSIM simulation is carried out and the experimental prototype is built to substantiate theoretical performance predictions. The simulation and experimental results are presented and compared. © The Institution of Engineering and Technology 2020Item A 61.2-dB?, 100 Gb/s Ultra-Low Noise Graphene TIA over D-Band Performance for 5G Optical Front-End Receiver(Springer, 2021) Gorre, P.; Vignesh, R.; Song, H.; Kumar, S.This work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-?m process. The TIA achieves a flat transimpedance gain of 61.2 dB? with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/?Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10?12 is achieved. The chip occupies an area of 0.92 * 1.34 mm2 while consuming power of 21 mW under supply of 1.8 V. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.Item Resonant DC/DC Converters: Investigating Phase-Shift Control(Multidisciplinary Digital Publishing Institute (MDPI), 2023) Reddy, V.B.; Mahajan, M.S.; Subramaniam, U.The paper presents an innovative approach to control the voltage of an LCL-T type converter at the output side against variation at input and load ports, utilizing a fixed-frequency phase-shift control scheme. The examination of the converter is performed employing a Fourier series method that takes into account the effect of n-harmonics. To assure high-frequency switches with a zero-voltage switching (ZVS) technique, the lagging pf mode is utilized. PSIM simulations were used to investigate the performance of a 300 W converter. With the minimal input voltage, all switches turn on with ZVS for all loading conditions, whereas the ZVS strategy loses by two switches when the voltage at the input is highest. The power loss calculations of each component are performed and presented in a pie chart. The findings of the experiments are presented and verified with theoretical and simulation results. It is demonstrated that for both input voltage and load fluctuations, a minor adjustment in pulse width is sufficient to keep the output voltage constant. © 2023 by the authors.