Faculty Publications
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Item Synthesis of BCH codes for enhancing data integrity in flash memories(2010) Rajesh Shetty, K.; Sripati, U.; Prashantha Kumar, H.; Shankarananda, B.Flash memories have found extensive application for use in portable storage devices. They have been used for code storage as well as data storage. The storage density associated with these devices has increased tremendously in the past few years. This has necessitated very dense packing of data bits on the device. This gives rise to increased Raw Bit Error Rate (RBER) as a result of Inter Symbol Interference (ISI) between bits stored in adjacent cells. This necessitates the use of powerful error control codes to guarantee information integrity. With the increase in density of data storage, the raw bit error rate (RBER) associated with the storage device increases. Error Control Coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes based on memory models proposed by the semiconductor industry. These codes have better error correcting capability than the codes used in current practice. ©2010 IEEE.Item Design and construction of BCH codes for enhancing data integrity in multi level flash memories(Inderscience Publishers, 2012) Rajesh Shetty, K.; Ramakrishna, K.; Prashantha Kumar, H.; Sripati, U.Flash memories have found extensive application for use in storage devices. The storage capacity and reliability of these devices have increased enormously over the years. With increase in density of data storage, the raw bit error rate (RBER), associated with the storage device increases. Error control coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes for flash memories based on multi level cell (MLC) concept. This is in continuation of our work on synthesis of BCH codes for improving the performance of flash memories based on single level cells (SLC). The improvement in device integrity resulting from the use of these codes has been quantified in this paper along with computation of parameters which allows modelling of flash memory as an equivalent channel. While synthesising codes, we have adhered to the limitations imposed by the memory architecture. Use of these codes in storage devices will result in considerable enhancement of device reliability and consequently open up many new applications for this class of storage devices. © 2012 Inderscience Enterprises Ltd.Item High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices(2012) Kumar, H.; Sripati, U.; Rajesh Shetty, K.In this article, we propose a high-speed decoding algorithm for binary BCH codes that can correct up to 7bits in error. Evaluation of the error-locator polynomial is the most complicated and time-consuming step in the decoding of a BCH code. We have derived equations for specifying the coefficients of the error-locator polynomial, which can form the basis for the development of a parallel architecture for the decoder. This approach has the advantage that all the coefficients of the error locator polynomial are computed in parallel (in one step). The roots of error-locator polynomial can be obtained by Chien's search and inverting these roots gives the error locations. This algorithm can be employed in any application where high-speed decoding of data encoded by a binary BCH code is required. One important application is in Flash memories where data integrity is preserved using a long, high-rate binary BCH code. We have synthesized generator polynomials for binary BCH codes (error-correcting capability, s) that can be employed in Flash memory devices to improve the integrity of information storage. The proposed decoding algorithm can be used as an efficient, high-speed decoder in this important application. © 2012 Taylor & Francis.Item On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories(Institute of Electrical and Electronics Engineers Inc., 2023) Achala, G.; Shripathi Acharya, U.S.; Srihari, P.The revolution in the field of information processing systems has created a huge demand for reliable and enhanced data storage capabilities. This demand is being met by advances in channel coding algorithms along with upward scaling of the capacities of hardware devices. NAND Flash memory is a type of non-volatile memory. Scaling of the size of flash memories from Single Level Cell (SLC) devices to Multilevel cell (MLC) devices has increased the storage capacity. However, these multi-bit per cell architectures are characterized by significantly higher Raw Bit Error Rate (RBER) values when compared with SLC architectures. The requirement of low Undetected Bit Error Rate (UBER) values has motivated us to synthesize powerful channel codes for enhancing the integrity of information Storage in multi-level NAND Flash Memory devices. This paper describes the synthesis of novel Subfield Subcodes of Reed Solomon Codes (SSRS) and Reed-Solomon (RS) codes which are matched to multi-bit per cell architectures. UBER values have been calculated for each of the synthesized codes described in this paper. This allows the determination of the performance and the improvement in data storage integrity brought by using these codes. We have shown that the synthesized SSRS and RS codes can provide very low UBER even when the corresponding RBER values are appreciable. As RS codes permit the detection and correction of a greater number of errors for a given code length, their performance is superior to that of SSRS codes. This improved performance is obtained at the cost of greater complexity of encoding and decoding processes. © 2013 IEEE.Item FPGA Implementation of SSRS Codes for NAND Flash Memory Device(Institute of Electrical and Electronics Engineers Inc., 2024) Achala, G.; Nandana, S.; Jomy, F.; Girish, M.M.; Shripathi Acharya, U.S.; Srihari, P.; Cenkarmaddi, L.R.NAND flash memory is a non-volatile storage device that is extensively used in personal electronic gadgets, digital television, digital cameras, and many consumer/ professional electronics devices. Error control coding techniques have been incorporated to improve the integrity of information stored in these devices. We have synthesized the Subfield Subcodes of Reed Solomon codes (SSRS) for use on Multi-Level cell (MLC), Triple Level Cell (TLC), and Quadruple Level Cell (QLC) NAND flash devices. The primary advantage of these codes is that the codeword symbols can be correctly matched to the number of bits that can be stored in these multilevel cells. Deployment of these codes improves the integrity of information storage and useful life. This paper describes the implementation of the encoder and decoder of SSRS codes synthesized for MLC, TLC, and QLC NAND flash devices. The encoder circuit is designed using addition and multiplication tables derived from elements of synthesized SSRS codes. The Non-binary decoding procedure consists of the syndrome computation, Berlekamp -Massey algorithm, Chein search, and Forney's algorithm. The designed encoder requires 16% resources for MLC, 18% of resources for TLC, and 18% of resources for QLC. This research work has reported the design of very high rate (R ≥ 0.97) codes that can bring about significant improvements to the Undetected Bit Error Rate (UBER) even when the Raw Bit Error rate (RBER) values are significant (> 10-3). © 2013 IEEE.