Faculty Publications

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Subject: search.filters.subject.Field programmable gate array

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    FPGA-Based Implementation of Backstepping Controller for Three-Phase Shunt Active Power Filter Interfacing Solar Photovoltaic System to Distribution Grid
    (Springer Science and Business Media Deutschland GmbH, 2021) Jayasankar, V.N.; Vinatha Urundady, U.
    The design and implementation of a controller for a solar photovoltaic system interfacing to the grid with shunt active power filter functionality are discussed in this paper. An inner harmonic current compensation loop and an outer dc voltage control loop constituted the control system. The inner loop is realized using a self-tuning filter (STF) based on instantaneous power theory, and the outer loop is realized using backstepping algorithm. The control algorithm is simulated under dynamic system conditions namely change in solar irradiation and change in load, in Matlab/Simulink environment. To ensure the effectiveness of the controller in mitigating the harmonic currents and interfacing solar PV system with distribution grid for real power exchange, the control algorithm is tested under steady-state and dynamic conditions and validated with the simulation results. The control algorithm is then implemented using a single all on-chip FPGA. Hardware co-simulation is carried out with the control system implemented in FPGA, and shunt active filter power circuit simulated in Matlab/Simulink. The hardware co-simulation results obtained are matching with the Matlab simulation results under dynamic system conditions and the controller design using FPGA is validated. © 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
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    Numerical and Experimental Investigations on Robust Output Feedback Control for Active Vibration Attenuation of Flexible Smart System
    (Institute of Electrical and Electronics Engineers Inc., 2023) Parameswaran, A.P.; Padmasali, A.N.; Gangadharan, K.V.
    This paper investigates the prototyping and implementation of an output feedback-based robust controller on a Field Programmable Gate Array (FPGA) platform. The Smart System under Test (SSuT) in this submission is a flexible cantilever beam bonded with Piezoelectric (PZT 5H) patches that act as a sensor as well as an actuator (perturbance creation as well as control actuation). For ease of modeling and subsequent controller design in the laboratory studies, the low-frequency dynamics of the smart system are approximated to only a Single Degree of Freedom (SDOF) in terms of flexural vibrations. The SSuT is modeled analytically through finite element modeling and experimentally through sub-space system identification process. The developed models' accuracy is compared with the experimental results of non - parametric modeling. The developed models are then used to conduct the simulation studies with the designed robust output feedback controller in the closed loop. Apart from the simulation studies, the designed controller was also prototyped on an FPGA platform using LabVIEW FPGA with the associated hardware in loop to carry out the experimental validation of its performance. The robustness and efficiency of the prototype controller to control the system vibrations in real-time were proved through extensive tests at single resonant frequencies and a range of frequencies encompassing the dominant resonant regions in the flexural mode. Findings from this study are further used to ensure satisfactory active vibration control of smart cantilever systems in various heavy/aerospace industries by approximating them to suitable benchmark systems in the laboratory. © 2013 IEEE.
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    Hardware Efficient Integrated In-loop Filter for HEVC Encoder
    (Taylor and Francis Ltd., 2024) Poola, L.; Aparna., P.
    The deblocking filter (DF) and the sample adaptive offset (SAO) filter, which aids in enhancing the subjective quality of the image, make up the in-loop filter of the high-efficiency video coding (HEVC) encoder and decoder. The in-loop filter significantly increases the computational load on the HEVC encoder. It is challenging to design an in-loop filter on hardware that can handle intensive computations while using the least amount of on-chip memory, taking external memory traffic and dependencies simultaneously delivering high throughput to support Ultra HD video applications. The proposed design employs the following strategies to address these issues. This work proposes an address generation technique for pipelined horizontal and vertical filtering in DF, that avoids a transpose buffer which otherwise is required. This enables easy pipelining and parallelization thus improving throughput while reducing the on-chip memory utilization. A simplified SAO filter with parallel-pipelined processing is included in the design. These features enable the design to support ultra-HD 7680 (Formula presented.) 4320 @ 40 fps video applications. The proposed hardware architecture has a total gate count of 7.73 K LUTs and 2.8 K slice registers, and it is implemented on a 28 nm field programmable gate array (FPGA) platform. © 2024 IETE.
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    FPGA implementation of deep learning architecture for kidney cancer detection from histopathological images
    (Springer, 2024) Lal, S.; Chanchal, A.K.; Kini, J.; Upadhyay, G.K.
    Kidney cancer is the most common type of cancer, and designing an automated system to accurately classify the cancer grade is of paramount importance for a better prognosis of the disease from histopathological kidney cancer images. Application of deep learning neural networks (DLNNs) for histopathological image classification is thriving and implementation of these networks on edge devices has been gaining the ground correspondingly due to high computational power and low latency requirements. This paper designs an automated system that classifies histopathological kidney cancer images. For experimentation, we have collected Kidney histopathological images of Non-cancerous, cancerous, and their respective grade of Renal Cell Carcinoma (RCC) from Kasturba Medical College (KMC), Mangalore, Karnataka, India. We have implemented and analyzed performances of deep learning architectures on a Field Programmable Gate Array (FPGA) board. Results yield that the Inception-V3 network provides better accuracy for kidney cancer detection as compared to other deep learning models on Kidney histopathological images. Further, the DenseNet-169 network provides better accuracy for kidney cancer grading as compared to other existing deep learning architecture on the FPGA board. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2023.