Faculty Publications

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Publications by NITK Faculty

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    VaFLE: Value flag length encoding for images in a multithreaded environment
    (Springer, 2019) Kinnal, B.; Pasupulety, U.; Geetha, V.
    The Run Length Encoding (RLE) algorithm substitutes long runs of identical symbols with the value of that symbol followed by the binary representation of the frequency of occurrences of that value. This lossless technique is effective for encoding images where many consecutive pixels have similar intensity values. One of the major problems of RLE for encoding runs of bits is that the encoded runs have their lengths represented as a fixed number of bits in order to simplify decoding. The number of bits assigned is equal to the number required to encode the maximum length run, which results in the addition of padding bits on runs whose lengths do not require as many bits for representation as the maximum length run. Due to this, the encoded output sometimes exceeds the size of the original input, especially for input data where in the runs can have a wide range of sizes. In this paper, we propose VaFLE, a general-purpose lossless data compression algorithm, where the number of bits allocated for representing the length of a given run is a function of the length of the run itself. The total size of an encoded run is independent of the maximum run length of the input data. In order to exploit the inherent data parallelism of RLE, VaFLE was also implemented in a multithreaded OpenMP environment. Our algorithm guarantees better compression rates of upto 3X more than standard RLE. The parallelized algorithm attains a speedup as high as 5X in grayscale and 4X in color images compared to the RLE approach. © Springer Nature Singapore Pte Ltd 2019.
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    New sparse matrix storage format to improve the performance of total SPMV time
    (2012) Bayyapu, B.; Raghavendra, S.R.; Guddeti, G.
    Graphics Processing Units (GPUs) are massive data parallel processors. High performance comes only at the cost of identifying data parallelism in the applications while using data parallel processors like GPU. This is an easy effort for applications that have regular memory access and high computation intensity. GPUs are equally attractive for sparse matrix vector multiplications (SPMV for short) that have irregular memory access. SPMV is an important computation in most of the scientific and engineering applications and scaling the performance, bandwidth utilization and compute intensity (ratio of computation to the data access) of SPMV computation is a priority in both academia and industry. There are various data structures and access patterns proposed for sparse matrix representation on GPUs and optimizations and improvements on these data structures is a continuous effort. This paper proposes a new format for the sparse matrix representation that reduces the data organization time and the memory transfer time from CPU to GPU for the memory bound SPMV computation. The BLSI (Bit Level Single Indexing) sparse matrix representation is up to 204% faster than COO (Co-ordinate), 104% faster than CSR (Compressed Sparse Row) and 217% faster than HYB (Hybrid) formats in memory transfer time from CPU to GPU. The proposed sparse matrix format is implemented in CUDA-C on CUDA (Compute Unified Device Architecture) supported NVIDIA graphics cards. © 2012 SCPE.
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    GPGPU-based randomized visual secret sharing (GRVSS) for grayscale and colour images
    (Taylor and Francis Ltd., 2022) Holla, R.; Mhala, N.C.; Pais, A.R.
    Visual Secret Sharing (VSS) is a technique used for sharing secret images between users. The existing VSS schemes reconstruct the original secret image as a halftone image with only a 50% contrast. The Randomized Visual Secret Sharing (RVSS) scheme overcomes the disadvantages of existing VSS schemes. Although RVSS extracts the secret image with better contrast, it is computationally expensive. This paper proposes a General Purpose Graphics Processing Unit (GPGPU)-based Randomized Visual Secret Sharing (GRVSS) technique that leverages data parallelism in the RVSS pipeline. The performance of the GRVSS is compared with the RVSS in a generic and PARAM Shavak supercomputer architecture. The GRVSS outperforms the RVSS in both architectures. © 2020 Informa UK Limited, trading as Taylor & Francis Group.