Faculty Publications
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Publications by NITK Faculty
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Item Applications nature aware virtual machine provisioning in cloud(Inderscience Publishers, 2018) Achar, R.; Santhi Thilagam, P.S.Rapid growth of internet technologies and virtualisation has made cloud as a new IT delivery mechanism, which is gaining popularity from both industry and academia. Huge demand for a cloud resources, running similar nature applications in the same server results in application degradation whenever there is a sudden rise in workload. In order to minimise the application degradations, there is an urgent need to know the nature of applications running in cloud for efficient virtual machine (VM) provisioning. Existing cloud architecture does not provide any mechanism to handle this issue. This paper presents a modified cloud architecture which contains additional component called application analyser to identify the nature of applications running in each VM. Based on applications nature, this paper presents a novel VM provisioning mechanism using genetic algorithm. In order to utilise the resources efficiently, this paper also presents a mechanism for VM provisioning with migration. Experimental study is conducted using CloudSim simulator shows that proposed mechanism is efficiently allocating resources to the virtual machines. © 2018 Inderscience Enterprises Ltd.Item Performance prediction of data streams on high-performance architecture(Springer Berlin Heidelberg, 2019) Gautam, B.; Annappa, A.Worldwide sensor streams are expanding continuously with unbounded velocity in volume, and for this acceleration, there is an adaptation of large stream data processing system from the homogeneous to rack-scale architecture which makes serious concern in the domain of workload optimization, scheduling, and resource management algorithms. Our proposed framework is based on providing architecture independent performance prediction model to enable resource adaptive distributed stream data processing platform. It is comprised of seven pre-defined domain for dynamic data stream metrics including a self-driven model which tries to fit these metrics using ridge regularization regression algorithm. Another significant contribution lies in fully-automated performance prediction model inherited from the state-of-the-art distributed data management system for distributed stream processing systems using Gaussian processes regression that cluster metrics with the help of dimensionality reduction algorithm. We implemented its base on Apache Heron and evaluated with proposed Benchmark Suite comprising of five domain-specific topologies. To assess the proposed methodologies, we forcefully ingest tuple skewness among the benchmarking topologies to set up the ground truth for predictions and found that accuracy of predicting the performance of data streams increased up to 80.62% from 66.36% along with the reduction of error from 37.14 to 16.06%. © 2019, The Author(s).Item LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA(Association for Computing Machinery acmhelp@acm.org, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.An FPGA-based Network-on-Chip (NoC) using a low-latency router with a look-ahead bypass (LBNoC) is discussed in this article. The proposed design targets the optimized area with improved network performance. The techniques such as single-cycle router bypass, adaptive routing module, parallel Virtual Channel (VC), and Switch allocation, combined virtual cut through and wormhole switching, have been employed in the design of the LBNoC router. The LBNoC router is parameterizable with the network topology, traffic patterns, routing algorithms, buffer depth, buffer width, number of VCs, and I/O ports being configurable. A table-based routing algorithm has been employed to support the design of custom topologies. The input buffer modules of NoC router have been mapped on the FPGA Block RAM hard blocks to utilize resources efficiently. The LBNoC architecture consumes 4.5% and 27.1% fewer hardware resources than the ProNoC and CONNECT NoC architectures. The average packet latency of the LBNoC NoC architecture is 30% and 15% lower than the CONNECT and ProNoC architectures. The LBNoC architecture is 1.15× and 1.18× faster than the ProNoC and CONNECT NoC frameworks. © 2020 Association for Computing Machinery.Item ELBA-NoC: Ensemble learning-based accelerator for 2D and 3D network-on-chip architectures(Inderscience Publishers, 2020) Kumar, A.; Talawar, B.Network-on-chips (NoCs) have emerged as a scalable alternative to traditional bus and point-to-point architectures, it has become highly sensitive as the number of cores increases. Simulation is one of the main tools used in NoC for analysing and testing new architectures. To achieve the best performance vs. cost trade-off, simulators have become an essential tool. Software simulators are too slow for evaluating large scale NoCs. This paper presents a framework which can be used to analyse overall performance of 2D and 3D NoC architectures which is fast and accurate. This framework is named as ensemble learning-based accelerator (ELBA-NoC) which is built using random forest regression algorithm to predict parameters of NoCs. On 2D, 3D NoC architectures, ELBA-NoC was tested and the results obtained were compared with extensively used Booksim NoC simulator. The framework showed an error rate of less than 5% and an overall speedup of up to 16 K×. © © 2020 Inderscience Enterprises Ltd.Item AMMDAS: Multi-modular generative masks processing architecture with adaptive wide field-of-view modeling strategy(Institute of Electrical and Electronics Engineers Inc., 2020) Desanamukula, V.S.; Chilukuri, P.K.; Padala, P.; Padala, P.; Pvgd, P.R.The usage of transportation systems is inevitable; any assistance module which can catalyze the flow involved in transportation systems, parallelly improving the reliability of processes involved is a boon for day-to-day human lives. This paper introduces a novel, cost-effective, and highly responsive Post-active Driving Assistance System, which is "Adaptive-Mask-Modelling Driving Assistance System" with intuitive wide field-of-view modeling architecture. The proposed system is a vision-based approach, which processes a panoramic-front view (stitched from temporal synchronous left, right stereo camera feed) & simple monocular-rear view to generate robust & reliable proximity triggers along with co-relative navigation suggestions. The proposed system generates robust objects, adaptive field-of-view masks using FRCNN+Resnet-101_FPN, DSED neural-networks, and are later processed and mutually analyzed at respective stages to trigger proximity alerts and frame reliable navigation suggestions. The proposed DSED network is an Encoder-Decoder-Convolutional-Neural-Network to estimate lane-offset parameters which are responsible for adaptive modeling of field-of-view range (1570-2100) during live inference. Proposed stages, deep-neural-networks, and implemented algorithms, modules are state-of-the-art and achieved outstanding performance with minimal loss(L{p, t}, L?, LTotal) values during benchmarking analysis on our custom-built, KITTI, MS-COCO, Pascal-VOC, Make-3D datasets. The proposed assistance-system is tested on our custom-built, multiple public datasets to generalize its reliability and robustness under multiple wild conditions, input traffic scenarios & locations. © 2020 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.Item Power and performance analysis of 3D network-on-chip architectures(Elsevier Ltd, 2020) Halavar, B.; Talawar, B.Emerging 3D integrated circuits(ICs) employ 3D network-on-chip(NoC) to improve power, performance, and scalability. The NoC Simulator uses the microarchitecture parameters to estimate the power and performance of the NoC. We explore the design space for 3D Mesh and Butterfly Fat Tree(BFT) NoC architecture using floorplan drive wire length and link delay estimation. The delay and power models are extended using Through Silicon Via (TSV) power and delay models. Serialization is employed to reduce the TSV area cost. Buffer space is equalised for a fair comparison between topologies. The Performance, Flits per Joules(FpJ) and Energy Delay Product(EDP) of six 2D and 3D variants of Mesh and BFT topologies (two and four layers) are analyzed by injecting synthetic traffic patterns. The 3D-4L Mesh exhibit better performance, energy efficiency (up to 4.5 × ), and EDP (up to 98 %) compared to other variants. This is because the overall length of the horizontal link is short and the number of TSVs is large (3 × ). © 2020 Elsevier LtdItem P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA(Springer, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall performance of CMPs and MPSoCs significantly. We propose P-NoC: an FPGA-based parameterized framework for analyzing the performance of NoC architectures based on various design decision parameters in this paper. The mesh and a multi-local port mesh (ML-mesh) topologies have been considered for the study. By fine-tuning various NoC parameters and synthesizing on the FPGA, identify that the performance of NoC architectures are influenced by the configuration of router parameters and the interconnect. Experiments show that the flit width, buffer depth, virtual channels parameters have a significant impact on the FPGA resources. We analyze the performance of the NoCs on six traffic patterns viz., uniform, bit shuffle, random permutation, transpose, bit complement and nearest neighbor. Configuring the router and the interconnect parameters, the ML-mesh topology yields 75% lesser utilization of FPGA resources compared to the mesh. The ML-mesh topology shows an improvement of 33.2% in network latency under localized traffic pattern. The mesh and ML-mesh topologies have 0.53× and 0.1× higher saturation throughput under nearest neighbor traffic compared to uniform random traffic. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item FPGA friendly NoC simulation acceleration framework employing the hard blocks(Springer, 2021) Prasad, B.M.P.; Parane, K.; Talawar, B.A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become the vehicle for simulation acceleration due to the properties of parallelism. Most of the state-of-the-art FPGA based NoC simulators utilize soft logic only for modeling the NoCs, leaving out the hard blocks to be unutilized. In this work, the FIFO Buffer and Crossbar switch functionalities of the NoC router have been embedded in the Block RAM (BRAMs) and the DSP48E1 slices with large multiplexer respectively. Employing the proposed techniques of mapping the NoC router components on the FPGA hard blocks, an NoC simulation acceleration framework based on the FPGA is presented in this work. A huge reduction in the use of the Configurable Logic Blocks (CLBs) has been observed when the FIFO buffer and Crossbar components of the NoC topology’s router micro-architecture are embedded in FPGA hard blocks. Our experimental results show that the topologies implemented employing the proposed FPGA friendly mapping of the NoC router components on the hard blocks consume 43.47% fewer LUTs and 41.66% fewer FFs than the topologies with CLB implementation. To optimize the latency of the NoC under consideration, a control unit called “buf_empty_checker” has been employed. A reduction in average latency has been observed compared to the CLB based topology implementation employing the proposed mapping. The proposed work consumes 10.88% fewer LUTs than the CONNECT NoC generation tool. Compared to DART, a reduction of 73.38% and 66.55% in LUTs and FFs has been observed with respect to the proposed work. The average packet latency of the proposed NoC architecture is 24.8% and 19.1% lesser than the CONNECT and DART architectures. © 2021, The Author(s), under exclusive licence to Springer-Verlag GmbH, AT part of Springer Nature.Item Fog-Based Intelligent Machine Malfunction Monitoring System for Industry 4.0(IEEE Computer Society, 2021) Natesha, B.V.; Guddeti, R.M.R.There is an exponential increase in the use of Industrial Internet of Things (IIoT) devices for controlling and monitoring the machines in an automated manufacturing industry. Different temperature sensors, pressure sensors, audio sensors, and camera devices are used as IIoT devices for pipeline monitoring and machine operation control in the industrial environment. But, monitoring and identifying the machine malfunction in an industrial environment is a challenging task. In this article, we consider machines fault diagnosis based on their operating sound using the fog computing architecture in the industrial environment. The different computing units, such as industrial controller units or micro data center are used as the fog server in the industrial environment to analyze and classify the machine sounds as normal and abnormal. The linear prediction coefficients and Mel-frequency cepstral coefficients are extracted from the machine sound to develop and deploy supervised machine learning (ML) models on the fog server to monitor and identify the malfunctioning machines based on the operating sound. The experimental results show the performance of ML models for the machines sound recorded with different signal-to-noise ratio levels for normal and abnormal operations. © 2021 IEEE.Item An integrated PMU architecture for power system applications(De Gruyter Open Ltd, 2022) Aalam, M.K.; Shubhanga, K.N.Time synchronized phasors obtained using Phasor Measurement Units (PMU) spread across wide areas have revolutionized power system monitoring and control. These synchronized measurements must be accurate and fast in order to comply with the latest IEEE standards for synchrophasor measurements. The speed at which a PMU provides an output depends on the group delay associated with that PMU and the permissible group delay in-turn decides the utility of a PMU for either control or measurement application. Based on the group delay compensation techniques, in the literature, two individual types of PMUs, such as causal and non-causal PMUs have been introduced. This paper presents an approach where both causal and non-causal PMUs are combined in an integrated PMU architecture. This method not only illustrates the group delay performance of two PMUs in a single module, but also can be used for multiple functions. In this environment several PMU algorithms have been compared with respect to their group delays and their effect on the response time. Application of the integrated PMU architecture to a four-machine 10-bus power system has been demonstrated using a six-input PMU with three-phase voltage and current signals as inputs. Different causal compensation schemes are introduced due to the availability of voltage and current-based frequency and ROCOF signals. Impact of these compensation schemes on PMU accuracy is evaluated through the Total Vector Error (TVE) index. The influence of these compensation schemes on measurements like power and impedance is also investigated. Finally, outputs from the integrated PMU architecture are fed into a Power System Stabilizer (PSS) to control the small-signal stability performance of a power system during dynamic conditions. © 2021 Walter de Gruyter GmbH, Berlin/Boston.