Faculty Publications
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Item A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system(Elsevier B.V., 2023) Kumar, K.; Kumar, S.; Kumar Kanaujia, B.K.This article reports a novel robust approach towards CMOS power amplifier (PA) using Quasi-newton (QN) control algorithm in 65 nm CMOS process which provides best performance parameters over redundant wide bandwidth ranging from 2.4 to 16.4 GHz frequency band. Each stage are designed and optimized using QN algorithm to get desired goals such as high linearity, small group delay variations and high PAE across the entire frequency band of interest. Moreover, pole-zeros compensation technique is adopted and derived to get better stability of the proposed PA. The simulation and measurement results of PA achieved a small signal power gain of 10.5–16.8 dB with input return loss of better than 10 dB over the frequency band of 2.4 GHz to 16.4 GHz. A small group delay variation of ±58 ps over full frequency band of operation is achieved by optimizing the design parametric analysis. It is also observed that within the frequency of 6.5 to 14.6 GHz, an excellent small group delay variation of only ±11 ps is achieved and this is due to stage-2 tuning compensation technique. It also demonstrates the achieved input power in 1 dB compression points are −3.1 to 4.3 dBm, leading to maximum power added efficiency of 36.3%, respectively. The proposed PA consumes a lower DC power of 20.5 mW under supply voltage of 1.5. In addition, Process, voltage and temperature (PVT) analysis is executed at different conditions in order to achieve a robustness of the proposed PA over the entire band of operation. © 2023 Elsevier B.V.Item Analytical modelling of ultra-small group delay variation of ultra-broadband RF power amplifier using NSGA-II algorithm(John Wiley and Sons Ltd, 2024) Kumar, K.; Kumar, S.; Kumar Kanaujia, B.K.This paper proposes a ± 9.4 ps ultra-small group delay (GD) variation of fully integrated 65 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) over 6.5–17 GHz broadband for wireless application. The proposed CMOS PA is realised by using broadband stage, RLC inter-stage and power stage topologies. The non-dominated sorting genetic algorithm (NSGA-II) is employed for PA parameter optimisation to ensure a small GD variation of ±9.4 ps over broadband with an excellent small signal gain flatness of 23.65 ± 1.85 for 6.5–17 GHz. The small GD variation of ±9.4 ps and ± 11.05 ps are attained under two cases of DC supply voltages of 2.4/1.2 V and 1.2/1.2 V, respectively. To the best of author's knowledge, the achieved GD variations are lowest among all CMOS PAs as reported so far. In addition, an analytical modelling of GD is derived to validating the minimum GD variation using zero-pole compensation. With supply voltages of 2.4/1.2 V at 6.5 GHz, the large signal power gain, Psat and OP1dB are 26 dB, 19.3 dBm and 17.94 dBm, respectively, while peak power added efficiency (PAE) is 38.196%. At reduced supply voltages of 1.2/1.2 V, the PA achieves maximum power gain of 17.7 dB and peak PAE of 35% at 6.5 GHz. The CMOS PA occupies an area of 0.206 mm2. © 2023 John Wiley & Sons Ltd.Item An Ultra-low Noise, Highly Compact Implantable 28 nm CMOS Neural Recording Amplifier(Institute of Electronics Engineers of Korea, 2024) Akuri, N.G.; Naik, D.N.; Kumar, S.; Song, H.; Kar, A.An ultra-low noise, Tera-ohm input impedance two-stage front-end neural amplifier (FENA) in the 28 nm CMOS process is presented in this work. As per the author’s best knowledge, the proposed FENA is implemented on a 28 nm CMOS process for the first time. The proposed FENA consists of an operational transconductance amplifier integrated low-pass filter (LPF) technique. This technique effectively removes the noise current density by using the LPF transfer function and FENA circuit to achieve the best performances, such as ultra-low input-referred noise, ultra-high input impedance, and high gain. The proposed mathematical technique is employed to optimize the dimensions of the neural amplifier in the 28 nm lower node, which results in a noise-free biasing current and ultra-low input referred noise of 18 fV/√Hz at 10 KHz. The ultra-low input referred noise of FENA is achieved by reducing the gate-distributed resistance method. The FENA achieves an ultra-high input impedance of 0.2 Tera-ohm, while a splendid measured gain of 60 dB has succeeded. FENA occupies a chip area of 0.0023 mm2, which consumes a lower power consumption of 1 µW under supply voltage of 1.2 V. The FENA is found to be less prone to PVT variations as 1 mHz of high-pass corner frequency towards robust design. The best performance parameters of FENA could be beneficial for deep exploration neural recording in wireless neural monitoring systems. © 2024, Institute of Electronics Engineers of Korea. All rights reserved.Item A 0.5–5 Gb/s Wide Range, 160 fJ/Pulse Fully Integrated 13th-Order CMOS IR-UWB Transmitter for Wireless Capsule Endoscopy Systems(John Wiley and Sons Ltd, 2025) Akuri, N.; Kumar, K.; Kumar, S.; Nikhil, K.S.; Song, H.This paper proposes a novel technique based fully integrated 13th-order derivative CMOS impulse-radio ultrawideband (IR-UWB) transmitter with wide range of adaptive data rates for wireless capsule endoscopy systems (WCE). The proposed IR-UWB transmitter involves BPSK modulator-integrated RF power amplifier (PA) approach for WCE in first time as per author's best knowledge. The CMOS BPSK modulator with resonator technique generates 13th-order Modulated Gaussian pulse without the pulse generator. It has a peak-to-peak value of 25 mV and PSD level of ?72.60 dBm/MHz, data rate variability from 500 Mbps to 5 Gbps. The BPSK modulator with resonator is designed by time constant analysis in first time. In addition, a proposed CMOS PA is designed using four stacked transistors, which achieves a high output power as well as high efficiency for entire frequency band of operation from 3 to 16 GHz and wide impedance matching. The PA achieved an excellent gain of 16.55 dB with gain ripple of 0.25 dB only. Moreover, the PA achieved the saturated output power of 18.2 to 19.3 dBm with OP1dB of 15.96 to 16.72 dBm across entire bandwidth. Without violating FCC guidelines, PA strengths both peak-to-peak values, and PSD level of BPSK modulated signal to 80 mV and ?46.42 dBm/MHz. An IR-UWB transmitter has been implemented and fabricated using 65-nm CMOS Process, which consumes of only 160 fJ/pulse for generating Gaussian pulses order ranging from third-order to more than 13th-order at various data rates. © 2025 John Wiley & Sons Ltd.