Faculty Publications

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Subject: search.filters.subject.Asynchronous design

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    A Comparative Analysis of Asynchronous and Synchronous NoC for Dynamic Traffic Handling using trace-inspired Synthetic Multimedia Data
    (Institute of Electrical and Electronics Engineers Inc., 2024) Saranya, M.N.; Avinash, C.T.; Rao, R.
    The paper investigates the feasibility of asynchronous Network-on-Chip (NoC) with wormhole switching in supporting traffic with variable data rates. A new approach to generate synthetic traffic close to realistic multimedia data traffic is also presented for the first time. This multimedia data stream traffic is utilized to evaluate the dynamic traffic handling capability of a generic synchronous NoC switch and asynchronous NoC switch architectures. Multimedia data streams are characterized as variable bit rate data streams where the amount of data being transmitted changes dynamically, depicting the heterogeneous timing of modern System-onChip (SoC). The Cadence Spectre Analog/Mixed Signal (AMS) Designer tool is used as a verification platform for the ease of simulation and to draw a fair comparison between the two architectures. The simulation platform is augmented with a real-time multimedia data stream for analysis. The simulation results show that the asynchronous design, activated only upon receiving data, outperforms the clock-triggered synchronous design in variable data-driven scenarios. © 2024 IEEE.
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    Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders
    (John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Girija Sravani, K.; Rao, R.
    This work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high-performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high-capacity hybrid (HC-hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC-180 nm and UMC-65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns. © 2020 John Wiley & Sons, Ltd.
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    Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems
    (Springer, 2024) Saranya, M.N.; Rao, R.
    The increasing multi-core system complexity with technology scaling introduces new constraints and challenges to interconnection network design. Consequently, the research community has a converging trend toward an asynchronous design paradigm for Network-on-Chip (NoC) architecture as a promising solution to these challenges. This paper addresses the design and functional verification aspects of an asynchronous NoC router microarchitecture for a Globally Asynchronous Locally Synchronous (GALS) system. Firstly, the paper introduces a novel mixed-level abstract simulation approach for faster functional verification of the asynchronous architecture using the commercially available Spectre Analog and mixed-signal simulation (AMS) Designer tool. This simulation methodology intends to ensure the feasibility of the design and identify shortcomings, if any, before the subsequent implementation stages of the design. Also, the paper proposes a new baseline asynchronous router built on a domino logic pipeline template with a novel hybrid encoding scheme. The new hybrid encoding scheme facilitates simple architecture with no additional timing constraints. The proposed verification methodology evaluates the baseline asynchronous router’s functional verification in Cadence’s AMS designer tool. Preliminary simulation results conform to the objectives of the paper. Further, the same verification setup establishes the design validation in subsequent stages of the design implementation. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.