Faculty Publications
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Publications by NITK Faculty
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Item A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC(2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, S.M.This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. © 2012 IEEE.Item Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC(Institute of Electrical and Electronics Engineers Inc., 2014) Jagadish, D.N.; Bhat, M.S.A low energy consumption and area efficient successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array (CA) in comparison to other nonbinary capacitor array based SAR ADCs. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside CA, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. © 2014 IEEE.Item A low-energy area-efficient dual channel SAR ADC using common capacitor array technique(Institute of Electrical and Electronics Engineers Inc., 2016) Reddy, N.S.; Jagadish, D.N.; Bhat, M.S.A novel low energy and area efficient Dual-Channel Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is presented. To achieve area efficiency, a common Capacitor Array (CA) technique is proposed wherein we use only N+1 CAs instead of 2N for N-channels in a differential architecture. In the present design we use three CAs instead of four for two channels. This reduction in CA count not only reduces the capacitance area but also the total energy required to charge and discharge the CAs. A 7-bit dual channel SAR ADC using the proposed technique is implemented in UMC 0.18μm CMOS technology. At a sampling rate of 4 MS/s and a supply voltage of 1.8 V, each channel consumes 43.85 μW and exhibits a FOM of 101.14 fJ/conversion step. © 2016 IEEE.Item An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC(Institute of Electrical and Electronics Engineers Inc., 2016) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.This paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 μW from the power supply of 1V. © 2015 IEEE.Item A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique(Springer Verlag, 2019) Polineni, S.; Bhat, M.S.; Rajan, A.A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology. © 2018, King Fahd University of Petroleum & Minerals.