Faculty Publications
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Item Low power ultra wide-band balun LNA using noise cancellation and current-reuse techniques(Elsevier Ltd, 2017) Vasudeva Reddy, K.; Girija Sravani, K.; Prashantha Kumar, P.A low power, single to differential (balun) low noise amplifier (LNA) using noise cancellation and current re-use techniques is presented for ultra wide-band applications. An upsurge balun LNA is designed using UMC 0.18-?m RF CMOS technology with an emphasis on the covenant between gain, bandwidth and power dissipation. The proposed balun exerts a differential stage on top of common gate-common source (CG-CS) stage. A CG-CS stage exploits amalgamation of CG stage (for wide-band impedance matching) and CS to curtail gain and phase imbalance, while simultaneously negating the noise and distortion of input matching transistor. The escalation of bandwidth has been accomplished using staggered tuning on CG-CS and differential stages. The stacked differential amplifier does cancellation of self noise as well as supply noise. The proposed UWB balun LNA achieves 14 dB voltage gain with agreeable input reverse isolation (S11) of <-8dB over the frequency range of 3.19–8.8 GHz. The minimum noise figure of 3.9 dB and P1dB of ?10.5 dBm while exhausting 3.8 mW from 1.2 V supply. The superlative performance of balun LNA is accomplished between 3.19 and 8.8 GHz with gain and phase errors below 0.2 dB and 0.40 respectively. The layout occupying 0.77 mm2 area. The overall pre and post layout simulations of proposed LNA shows admissible agreement with theoretical predictions. © 2017 Elsevier LtdItem PVT compensated high selectivity low-power balun LNA for MedRadio communication(Institution of Engineering and Technology journals@theiet.org, 2018) Vasudeva Reddy, V.R.; Herolli, P.K.; Shojaei Baghini, M.S.A single-to-differential low-noise amplifier (LNA) is proposed for low-power medical devices in the frequency band of 401-406 MHz. The proposed LNA avoids the use of surface acoustic wave (SAW) filter and additional balun in RF receiver front-end. The LNA comprises inductive degeneration common source (IDCS) technique (stage I) and a cascaded common source circuit (stage II). The stage-II is stacked on top of stage-I. The proposed balun LNA incorporates single to differential (SD) conversion for minimum gain and phase error. A compensation bias circuit is proposed to minimise variations in parameters of LNA against process corners, supply voltage and temperature (PVT). An upsurge balun LNA is designed in UMC 0.18-?m CMOS technology, the DC power consumption is 290 ?W under a supply voltage of 1 V and the minimum noise figure is 3 dB. The die area of LNA including buffers and bias circuit is 850 ?m × 978 ?m. The worst-case post layout simulation results show a gain and phase error of 0.8 dB and 10°. The percentage variation of gain and NF against PVT is reduced by 55 and 48%. Furthermore, the balun LNA has out of band rejection at the roll-off rate better than 70 dB/dec. © 2018, The Institution of Engineering and Technology.Item Investigation of CMOS Based Integration Approach Using DAI Technique for Next Generation Wireless Networks(Springer New York LLC barbara.b.bertram@gsk.com, 2019) Roy, G.M.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.This research work investigates a CMOS based low noise amplifier (LNA) using differential active inductor with eight-shaped patch antenna for next generation wireless communication. The proposed work conceded into three different phases. The first phase proposes LNA architecture which includes multistage cascode amplifier with a gate inductor gain peaking technique. The ground approach for this architecture employs active inductor technique that includes two stages of differential amplifier. The proposed novel technique leads to give incremental in inductance by using of common mode feedback resistor and lowers the undesirable parasitic resistance effect. Additionally, this technique offers gain enhanced noise cancellation and achieves a frequency band of around 5.7 GHz. The proposed architecture includes single stage differential AI and enhances the bandwidth up to 6.8 GHz with peak gain of 21 dB at 7.8 GHz. The noise figure and stability factor are achieved which is reasonably good at 1 dB. The proposed architecture is design and optimized on advanced design RF simulator using 0.045 µm CMOS process technology. While in second phase, a narrow band eight-shaped patch antenna is designed which provides operating band range from 5.8 to 6.5 GHz with 6.2 GHz resonating frequency. Highest peak gain of 15 dB and maximum radiation power of 42.5 dBm is succeed by proposed antenna. The final phase provides integration strategy of LNA with antenna and achieves desired gain of nearly 21 dB with minimum NF of 1.2–1.5 dB in the same band. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.Item Inductor-less PVT robust gain switching balun LNA for multistandard applications(Taylor and Francis Ltd. michael.wagreich@univie.ac.at, 2019) Vasudeva Reddy, K.; Prashantha Kumar, H.An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g m is not more than 10%. The proposed LNA is implemented in UMC 0.18-?m RF CMOS technology. The core area is 182 ?m × 181 ?m. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3? deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations. © 2019, © 2019 Informa UK Limited, trading as Taylor & Francis Group.Item Performance analysis of 65 nm CMOS LNA using SSL technique for 5G cellular front-end receivers(Elsevier GmbH k.ernst@elsevier.com, 2020) R, V.; Gorre, P.; Song, H.; Kumar, S.This paper presents a performance analysis of a wideband low noise amplifier (LNA) that utilizes a 65 nm CMOS Samsung mm-wave process. The proposed CMOS LNA designed with new built-in techniques will overcome the challenges faced by device parasitic and electromagnetic (EM) losses. A suspended substrate line (SSL) is characterized and analyzed with its dual-band operation and achieves excellent EM compatibility. The traditional EM losses in bulk active and passive components have been incurred using built-in techniques to provide better linearity of LNA. The proposed mm-wave LNA enables it's each family component to avoid leakage of EM waves and its interconnected parasitic losses in layout. An SSL based parallel-series network is optimized to achieve a wide bandwidth of 26 GHz to 34 GHz. The full design of LNA achieves the highest peak gain of 25 dB by using proper 50 ? matching constraints over the wideband response of 27.8 GHz to 32.5 GHz. The fabricated chip of LNA is given a supply voltage of 1.2 V, and the calculated chip area is 0.35*0.22 mm2. The simulation and measurement results demonstrate the minimum noise figure of 2.5 dB and achieve the highest stability factor in the desired band of operation. The LNA also measured linearity with a 1 dB compression point where input power of ?19dBm has obtained at 30.5 GHz. © 2020 Elsevier GmbHItem Active feedback supported CMOS LNA blended with coplanar waveguide-fed antenna for Wi-Fi networks(John Wiley and Sons Inc, 2021) Roy, G.M.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi-Fi networks. The LNA design-I, involves a cascode amplifier followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor-less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design-II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign-III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost. © 2021 The Authors. IET Microwaves, Antennas & Propagation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.Item Highly robust X-band quasi circulator-integrated low-noise amplifier for high survivability of radio frequency front-end systems(John Wiley and Sons Ltd, 2021) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.In this brief, an X-band quasi circulator (QC)-integrated low-noise amplifier (LNA) implemented in 65-nm Complementary Metal Oxide Semiconductor (CMOS) technology is presented. This work is the first QC-LNA for the X-band to the author's best knowledge, which achieves 30-dB flat gain in 8–12 GHz with only 0.5-dB variation across the band. This QC-LNA uses two-stage current reused techniques with variable impedance load. QC provides the minimum insertion loss of 0.9 dB with good return and isolation losses. Statistical analysis is presented for QC-LNA to predict the percentage error tolerance. Quasi-Newton (QN) control algorithm is used to optimize the parameter of the whole design. The design of experiment (DoE) is performed to claim the contribution towards gain, return loss, and noise figure. The proposed LNA measurement provides a minimum NF of 1 dB at 9.5 GHz, which remains less than 1.4 dB across 8–12 GHz. The fabricated LNA works with a supply voltage of 1.2 V and is unconditionally stable across the frequency. The calculated chip area is 0.84 × 0.52 mm2. This QC-LNA exhibits an input and output 1-dB compression point (IP1dB and OP1dB) of ?15 and +13.8 dBm, respectively. It also exhibits third-order input and output intercept point (IIP3 and OIP3) of +10 dBm and of +40 dBm, respectively. The proposed QC-LNA draws only 8.7 mA from 1.2 V. © 2021 John Wiley & Sons, Ltd.Item A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line(Institute of Electrical and Electronics Engineers Inc., 2022) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author's best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band's drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP1dB OP1dB), third-order input output intercept point (IIP3 OIP3) of -17/-16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61 $\times $ 0.92 mm2. © 2013 IEEE.Item A wideband, 25/40dBm high I/O power GaN HEMT ultra-low noise amplifier using even-odd mode techniques(Elsevier Ltd, 2022) Gupta, M.P.; Gorre, P.; Kumar, S.; Nulu, V.This paper presents a performance analysis of the low noise amplifier (LNA) for the first time using even-odd mode matching techniques in Gallium Nitride (GaN) HEMT Technology for marine communication. The proposed GaN LNA circuit consists of broadband stage I, main amplifier, and inverted broadband stage II, which provides a high input/output power, and ultra-low noise over wide bandwidth ranging from 0.5 GHz to 2.7 GHz with fractional impedance bandwidth of 138%. Broadband Stage I and Inverted broadband stage II are employed to provide input/output impedance matching transformation. The proposed LNA circuit with the incorporation of input/output broadband stages relax a 50Ω matching constraints and achieved high input and output power with good stability. The GaN HEMT LNA is analyzed and simulated using the RF simulator (ADS tool). The proposed GaN HEMT LNA is fabricated on RT Duroid substrate using Microwave Integrated Circuit (MIC) technology. The proposed LNA achieves a measured gain of 16 dB, while the simulated one is 17 dB with good insertion loss. An ultra-low noise figure of 0.6 dB flat is achieved over a wide bandwidth. In addition, the high output power is achieved 40dBm while input power is 25dBm which could overcome weak signal strength received by RF receiver for marine communication. A stability factor greater than one is achieved over a broad band ranging from 0.5 GHz to 2.7 GHz. The fabricated GaN HEMT LNA circuit has consumed power of 120 mW under a supply of 28 V. The area of the fabricated RF GaN HEMT LNA is 32 × 26 mm2. © 2022 Elsevier LtdItem A 0.15 μm GaN HEMT device to circuit approach towards dual-band ultra-low noise amplifier using defected ground bias technique(Elsevier GmbH, 2023) Gupta, M.P.; Kumar, S.; Elizabeth Caroline, B.; Song, H.; Kumar, V.; Gorre, P.This work presents a GaN HEMT device to circuit approach towards low noise amplifier (LNA) using defective ground bias (DGB) technique. This is the first MMIC GaN HEMT LNA design to offer dual-band of operation in both L and S-bands to the author's best knowledge. The proposed 0.15-μm GaN HEMT device fabrication achieves a high output power of 20 W using slot radiation phenomenon. The proposed DGB technique consists of gate and drain biasing topologies which achieves a dual-band of operation using microwave approach. The DGB technique is incorporated into GaN HEMT LNA which achieves high input and output power with good stability. To achieve an optimal noise, high I/O power, and almost flat gain at both L and S-bands, the defective ground structure of bias topologies is modeled and optimized. An artificial ground defect is created to offer resonant properties for the DGS of a microstrip line, which utilizes frequency-selective properties to improve the performance of the LNA circuit by suppressing the harmonics and scaling the size. The dedicated LNA shows the benefits of compact size, extremely low noise figure of 0.74/1.6 dB, high output power of 44 dBm and nearly flat gain of 14/11 dB at 1.17/2.49 GHz with the unique methodologies suggested. The compact GaN HEMT LNA could overcome the weak signal strength received by RF receiver for smart rail transport system. © 2023 Elsevier GmbH