Faculty Publications

Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736

Publications by NITK Faculty

Browse

Has files: NoSubject: search.filters.subject.Field programmable gate arrays (FPGA)

Search Results

Now showing 1 - 10 of 26
  • No Thumbnail Available
    Item
    FPGA based vibration control of a mass varying two-degree of freedom system
    (Exeley Inc, 2011) Singh, M.P.; Tripathi, P.K.; Gangadharan, K.V.
    Controlling of vibration in any system is very challenging problem. In the present work design, fabrication and testing of a variable mass 2-DoF system was presented. The system has been designed to be used as tool to demonstrate the capability of mass variable tuned vibration damper for wide frequency application. All valves and pumps were controlled by a cRIO with onboard FPGA. cRIO with FPGA enable the designer to implement different control algorithms that can be used for real time wide spectrum vibration control. LabVIEW with real time suite was used for algorithm implementation and device control. To avoid sloshing in tanks at different water height a floating roof was used. Its effect on damping was also studied.
  • No Thumbnail Available
    Item
    Performance analysis of energy efficient modulation and coding schemes for wireless sensor networks
    (2013) Shivaprakasha, K.S.; Kulkarni, M.; Patkar, R.
    Sensor nodes of a typical wireless sensor network (WSN) are battery driven, so energy conservation is a critical factor for node's life time. Thus optimisation of energy consumption is a major objective in the area of WSNs. One such method is asymmetric communication which uses different channel codes and modulation schemes for downlink (base station (BS) to node link) and uplink (node to BS link). In this paper, a performance analysis of different channel code-modulation pair for energy efficient asymmetric communication is carried out followed by the field programmable gate array implementation of channel codes required at the node. The per information bit node energy for the uplink has been calculated for efficient channel code-modulation pair, for three different channels, viz. additive white gaussian noise, Rayleigh flat-fading and log-normal shadowing channels, resulting in reduction in energy consumption at sensor nodes. © 2013 Copyright Taylor and Francis Group, LLC.
  • No Thumbnail Available
    Item
    Modeling and design of field programmable gate array based real time robust controller for active control of vibrating smart system
    (Academic Press, 2015) Parameswaran, A.P.; Ananthakrishnan, B.; Gangadharan, K.V.
    The current paper focuses on accurate mathematical modeling of a vibrating piezoelectric laminate cantilever beam theoretically as well as experimentally so as to obtain the best replication of the system dynamics on the software platform for simulation studies. The developed models were tested for accuracy in time as well as frequency domain by employing the sweep sine test. The focus of the study is on the flexural modes of vibrations of the cantilever beam. Here, modeling is focused on the first vibratory mode as it has been observed that the effects of felt vibrations would be maximum in terms of system stability and its operational efficiency when the excitation frequency matches with the first natural frequency of the system (fn1). This was validated by appropriate non-parametric modeling of the smart system by subjecting it to the Impact Hammer test. Development of accurate system models play an important role in designing and testing various control algorithms for reliable active vibration control (AVC). In the final stage, a real time active vibration robust controller was designed using a proportional derivative sliding mode control (PDSMC) technique and deployed on a Field Programmable Gate Array (FPGA) platform. The efficiency of the developed real time controller was proved in time as well as frequency domains by subjecting the closed loop system to harmonic excitations at first natural frequency as well as sweep sine test focussing on the first vibratory mode with the conclusion that the developed controller will function satisfactorily at higher modes of vibrations. © 2015 Elsevier Ltd.
  • No Thumbnail Available
    Item
    Design and development of a model free robust controller for active control of dominant flexural modes of vibrations in a smart system
    (Academic Press, 2015) Parameswaran, A.P.; Ananthakrishnan, B.; Gangadharan, K.V.
    Real physical vibrating smart systems exhibit a lot of nonlinearities in their dynamics. Undesirable vibrations, particularly in the regions of first as well as second resonance, play a very important role in deteriorating the stability of the system as well as its operational efficiency. The work presented in the paper focuses on an analytical technique of mathematical modeling of a vibrating piezoelectric laminate cantilever beam which is considered to be the smart system. The natural frequencies of the vibrating smart system are determined from the ANSYS simulation studies and experimentally, it is found that the vibrations induced voltage is maximum at the first followed by the second natural frequencies. Hence, the smart system is modeled analytically through finite element technique using the Euler-Bernoulli beam theory for the first two flexural modes of vibrations. To account for the possible nonlinearities, a suitable robust controller is designed based on sliding mode technique. Simulation studies on the developed analytical model indicated a high performance of the designed controller in controlling the vibrations at first and second resonance regions. Also, the designed controller was found to be effective in its operations when the excitation varied over a large range covering the first two natural frequencies. In the final stage, the designed robust controller was successfully prototyped on a Field Programmable Gate Array (FPGA) platform using LabVIEW coupled with Compact Reconfigurable Input Output (cRIO-9022) controller configured in its FPGA interface mode and the resulting robust FPGA controller successfully controlled the occurring system vibrations. © 2015 Elsevier Ltd.
  • No Thumbnail Available
    Item
    Parametric modeling and FPGA based real time active vibration control of a piezoelectric laminate cantilever beam at resonance
    (SAGE Publications Inc., 2015) Parameswaran, A.P.; Gangadharan, K.V.
    The operational efficiency and life of mechanical systems/structures depends to a large extent on their vibration control. Continuously occurring vibrations on the systems can cause fatigue and the effects of these vibrations are particularly severe if they occur at a frequency matching with that of the concerned systems natural frequency - a stage called resonance. This paper focuses on achieving active vibration control of a smart cantilever beam at its first resonant frequency as it is at this stage that maximum damage to the system performance is expected. The smart system is modelled in the parametric domain using finite element modeling techniques and the obtained model is validated through experimental means. The active vibration control is achieved by employing two control algorithms namely - output feedback and error based control through general purpose operating system (LabVIEW on Windows 7) as well as in real time operating system (LabVIEW FPGA coupled with compact reconfigurable input output modules) and the performances are compared thereby justifying the importance of the deterministic and reliable real time control over the usual PC based control in experimental studies. © The Author(s) 2014.
  • No Thumbnail Available
    Item
    Laboratory implementation of electromagnetic torque based MRAS speed estimator for sensorless SMPMSM drive
    (Institution of Engineering and Technology JBristow@theiet.org, 2019) Koothu Kesavan, K.; Karthikeyan, A.; Blaabjerg, F.
    This Letter proposes a simple electromagnetic torque based model reference adaptive system (MRAS) speed estimator for sensorless surface mount permanent magnet synchronous motor (SMPMSM) drive. The proposed estimator is formed using instantaneous measured and estimated electromagnetic torque. The proposed estimator is implemented for 1.5 kW laboratory prototype SMPMSM drive using field programmable gate array ALTERA cyclone II. Experimental results demonstrate the efficacy of the proposed scheme under different test conditions viz. different low-speed regions and standstill at different load conditions with uncertainty in machine parameters. Results show that the estimator is stable in low-speed regions and exhibits robustness against uncertainties in machine parameters. © The Institution of Engineering and Technology 2019
  • No Thumbnail Available
    Item
    YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAS
    (World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2019) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
    Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the 6×6 mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the 6×6 mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively. © 2019 World Scientific Publishing Company.
  • No Thumbnail Available
    Item
    FPGA based direct torque control with speed loop Pseudo derivative controller for PMSM drive
    (Springer, 2019) Karthikeyan, A.; Koothu Kesavan, K.; Nagamani, C.
    This paper presents a comprehensive evaluation of proposed speed loop pseudo derivative feedback (PDF) controller based DTC with speed loop PI based direct torque controller (DTC) for permanent magnet synchronous motor (PMSM) drive. The proposed PDF-DTC system significantly improves dynamic response i.e. completely eliminates overshoot in speed, reduces 50% overshoot in electromagnetic torque and has two times faster settling time compared to PI-DTC system during step changes in speed with load disturbance. The proposed controller is verified for different cases viz., speed variation at constant load and variation in the load torque at constant speed. The proposed controller is implemented for 1.5 kW laboratory prototype PMSM drive using FPGA ALTERA cyclone II. Experimental results demonstrates the efficacy of the proposed controller. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.
  • No Thumbnail Available
    Item
    LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
    (Association for Computing Machinery acmhelp@acm.org, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
    An FPGA-based Network-on-Chip (NoC) using a low-latency router with a look-ahead bypass (LBNoC) is discussed in this article. The proposed design targets the optimized area with improved network performance. The techniques such as single-cycle router bypass, adaptive routing module, parallel Virtual Channel (VC), and Switch allocation, combined virtual cut through and wormhole switching, have been employed in the design of the LBNoC router. The LBNoC router is parameterizable with the network topology, traffic patterns, routing algorithms, buffer depth, buffer width, number of VCs, and I/O ports being configurable. A table-based routing algorithm has been employed to support the design of custom topologies. The input buffer modules of NoC router have been mapped on the FPGA Block RAM hard blocks to utilize resources efficiently. The LBNoC architecture consumes 4.5% and 27.1% fewer hardware resources than the ProNoC and CONNECT NoC architectures. The average packet latency of the LBNoC NoC architecture is 30% and 15% lower than the CONNECT and ProNoC architectures. The LBNoC architecture is 1.15× and 1.18× faster than the ProNoC and CONNECT NoC frameworks. © 2020 Association for Computing Machinery.
  • No Thumbnail Available
    Item
    Electromagnetic torque-based model reference adaptive system speed estimator for sensorless surface mount permanent magnet synchronous motor drive
    (Institute of Electrical and Electronics Engineers Inc., 2020) Koothu Kesavan, K.K.; Karthikeyan, A.
    This article proposes simple and robust electromagnetic torque-based model reference adaptive system speed estimator with cascaded pseudoderivative feedback controller for sensorless surface mount permanent magnet synchronous motor (SMPMSM) drive to improve its performance at standstill and low-speed regions. The proposed estimator is formed using instantaneous and estimated electromagnetic torque. Using small signal modeling, the stability and sensitivity analysis are performed. Results show that the estimator is stable over a wide speed region (including low-speed regions) and exhibits robustness against uncertainties in machine parameters. The proposed estimator is implemented for the 1.5-kW laboratory prototype SMPMSM drive using field programmable gate array (FPGA) ALTERA Cyclone II. Experimental results demonstrate the efficacy of the proposed scheme under different test conditions viz., over a wide adjustable speed range which includes different low-speed regions and standstill, i.e., 157 to -157 rad/s at different load conditions with uncertainty in machine parameters. © 1982-2012 IEEE.