Faculty Publications

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Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures
(Elsevier B.V., 2019) Halavar, B.; Pasupulety, U.; Talawar, B.
With the increase in number and complexity of cores and components in Chip-Multiprocessors (CMP) and Systems-on-Chip (SoCs), a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network-on-Chip (NoC) has emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. Cycle accurate simulators model the functionality and behaviour of NoCs by considering micro-architectural parameters of the underlying components to estimate performance, power and energy characteristics. Employing NoCs in three-dimensional integrated circuits (3D-ICs) can further improve performance, energy efficiency, and scalability characteristics of 3D SoCs and CMPs. Minimal error estimation of energy and performance of NoC components is crucial in architecture trade-off studies. Accurate modeling of re:Horizontal and vertical links by considering micro-architectural and physical characteristics reduces the error in power and performance estimation of 3D NoCs. Additionally, mapping the temperature distribution in a 3D NoC reduces estimation error. This paper presents the 3D NoC modelling capabilities extended in two existing state-of-the-art simulators, viz., the 2D NoC Simulator - BookSim2.0 and the thermal behaviour simulator - HotSpot6.0. With the extended 3D NoC modules, the simulators can be used for power, performance and thermal measurements through micro-architectural and physical parameters. The major extensions incorporated in BookSim2.0 are: Through Silicon Via power and performance models, 3D topology construction modules, 3D Mesh topology construction using variable X, Y, Z radix, tailored routing modules for 3D NoCs. The major extensions incorporated in HotSpot6.0 are: parameterized 2D router floorplan, 3D router floorplan including Through Silicon Vias (TSVs), power and thermal distribution models of 2D and 3D routers. Using the extended 3D modules, performance (average network latency), and energy efficiency metrics (Energy-Delay Product) of variants of 3D Mesh and 3D Butterfly Fat Tree topologies have been evaluated using synthetic traffic patterns. Results show that the 4-layer 3D Mesh is 2.2 × better than 2-layer 3D Mesh and 4.5 × better than 3D BFT variants in terms of network latency. 3D Mesh variants have the lowest Energy Delay Product (EDP) compared to 3D BFT variants as there is an 80% reduction in link lengths and up to 3 × more TSVs. Another observation is that the EDP of the 4-layer 3D BFT (with transpose traffic) is 1.5 × the EDP of the 4-layer 3D Mesh (with transpose traffic). Further optimizations towards a tailored 3D BFT for transpose traffic could reduce this EDP gap with the 4-layer 3D Mesh. From the 3D NoC heat maps, it was found that the edge routers in the floorplan of the tested 3D Mesh and 3D BFT topologies have the least ambient temperature. © 2019
Power and performance analysis of 3D network-on-chip architectures
(Elsevier Ltd, 2020) Halavar, B.; Talawar, B.
Emerging 3D integrated circuits(ICs) employ 3D network-on-chip(NoC) to improve power, performance, and scalability. The NoC Simulator uses the microarchitecture parameters to estimate the power and performance of the NoC. We explore the design space for 3D Mesh and Butterfly Fat Tree(BFT) NoC architecture using floorplan drive wire length and link delay estimation. The delay and power models are extended using Through Silicon Via (TSV) power and delay models. Serialization is employed to reduce the TSV area cost. Buffer space is equalised for a fair comparison between topologies. The Performance, Flits per Joules(FpJ) and Energy Delay Product(EDP) of six 2D and 3D variants of Mesh and BFT topologies (two and four layers) are analyzed by injecting synthetic traffic patterns. The 3D-4L Mesh exhibit better performance, energy efficiency (up to 4.5 × ), and EDP (up to 98 %) compared to other variants. This is because the overall length of the horizontal link is short and the number of TSVs is large (3 × ). © 2020 Elsevier Ltd
Effect of Ni nanoparticles reinforcement on wettability, microstructure and mechanical properties of SAC387 lead-free solder alloy
(Elsevier Ltd, 2025) Muhammed, H.J.; Prabhu, K.N.
The study investigates the influence of nickel (Ni) nanoparticles on the wettability, microstructure, and mechanical properties of Sn-3.8Ag-0.7Cu (SAC387) lead-free solder alloy. Nanocomposite solders containing 0.3 wt% and 0.5 wt% Ni were prepared and reflowed at temperatures of 230 °C, 250 °C, and 270 °C to evaluate their performance on copper substrates with a surface roughness (Ra) of 0.01 ± 0.002 ?m. Wettability improved with increasing reflow temperature; however, the addition of Ni nanoparticles had minimal direct impact on spreading behavior. Microstructural analysis revealed enhanced formation of interfacial intermetallic compounds (IMCs), particularly (Cu,Ni)6Sn5 which contributed to improved joint stability. The optimal mechanical performance was observed at 250 °C with 0.3 wt% Ni addition, yielding a 51.14 % increase in shear strength compared to the unreinforced solder. Microhardness also improved significantly by 43.7 % at the IMC layer and 18.3 % in the solder bulk. Weibull analysis further confirmed higher joint performance with Ni nanoparticle incorporation. These findings highlight the potential of addition of Ni nanoparticles in improving the performance of SAC387 solder joints in electronic packaging. © 2025 Elsevier Ltd

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