Faculty Publications

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    Design and development of current source fed full-bridge DC-DC converter for (60V/50A)telecom power supply
    (Institute of Electrical and Electronics Engineers Inc., 2018) Kalpana, R.; Kiran, R.
    This paper addresses a dual input converter (DIC) for telecom power system of 3 kW using digital control algorithm. The proposed system gives an alternative way of fusing the sources of DC in magnetic form, instead of combining in the DC electrical form, by the addition of magnetic flux that is produced in the transformer magnetic core, which works on the principle of flux additivity. A detailed design, operation and control strategy of the proposed dual input isolated full-bridge step down DC-DC converter has been completely evaluated and presented in this paper. A constant frequency phase shifted PWM switching strategy have been preferred for the generation of gate pulses using FPGA controller board. The simulation analysis of the proposed converter has been executed utilizing MATLAB Simulink environment. A prototype for the proposed converter of 1.5 kW has been developed and experimental results are presented to validate the theoretical waveform of the proposed converter. © 2017 IEEE.
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    Digital Control System Based Isolated Totem Pole Converter for Electric Vehicle Onboard Chargers
    (Institute of Electrical and Electronics Engineers Inc., 2025) Das, A.K.; Raushan, R.; Kumar, P.
    The Totem-Pole converter is well-suited for lowpowered electric vehicle (EV) applications. The isolated configurations of such converters provide single-stage power conversion that overcomes the more conversion stages. A robust controller can satisfy the converter operations efficiently for on-board charging applications. In this paper, a modified digital control method for totem-pole PFC cascaded active flyback DC-DC converters functioning in discontinuous conduction mode (DCM) is proposed. The auxiliary switch and clamp capacitor are used to recycle the stored energy in the transformer to reduce the spike voltage. The main purpose of adding PFC is to obtain the input current in phase with the input voltage, keeping total harmonic distortion (THD) low to improve the efficiency of the converter. © 2025 IEEE.
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    Synchronized symmetrical bus-clamping PWM strategies for three level inverter: Applications to low switching frequencies
    (2011) Veeranna, S.B.; Yaragatti, U.R.; Beig, A.R.
    The digital control of three-level voltage source inverter fed high power high performance ac drives has recently become a popular in industrial applications. In order to control such drives, the pulse width modulation algorithm needs to be implemented in the controller. In this paper, synchronized symmetrical bus-clamping pulse width modulation strategies are presented. These strategies have some practical advantages such as reduced average switching frequency, easy digital implementation, reduced switching losses and improved output voltage quality compared to conventional space vector pulse width modulation strategies. The operation of three level inverter in linear region is extended to overmodulation region. The performance is analyzed in terms THD and fundamental output voltage waveforms and is compared with conventional space vector PWM strategies and found that switching losses can be minimized using bus-clamping strategy compared to conventional space vector strategy. The proposed method is implemented using Motorola Power PC 8240 processor and verified on a constant v/f induction motor drive fed from IGBT based inverter. © 2011 Berkeley Electronic Press. All rights reserved.
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    Fast start crystal oscillator design with negative resistance control
    (Elsevier B.V., 2019) Kumar, P.; Rekha, S.
    Clock is an essential part of most of the integrated circuits as time base reference. It must be very accurate, highly reliable and readily available as soon as it is enabled. In all types of oscillator architectures, crystal oscillator is the most accurate and stable clock generator. But usually the crystal oscillator circuit suffers from slow startup. Therefore, it is essential to improve the startup time with optimally controlled crystal drive such that crystal drive power rating is not compromised. We propose a method that discusses about increasing the negative resistance during startup, using a startup circuit for fast start. Once the reliable startup is achieved, the negative resistance is decreased and the startup circuit is disconnected. The reduction in negative resistance is done with current steps and there are two ways in which it is achieved, the Digital control method and Analog control method. In digital control method, the current steps are timed at regular intervals and in analog control method, oscillator output amplitude is given as feedback to the startup circuit there by reducing the negative resistance. In the 32768 Hz real time clock generating oscillator, the startup time can be improved from 330 ms to 220 ms using the conventional startup method. With the proposed digital control method, lesser startup time of 160 ms is achieved and in analog control method it is further reduced to 120 ms. © 2018 Elsevier B.V.
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    A Systematic Approach to Digital Control Development for Four-Phase SRM Drive Using Single Current Sensor for Medium Power Applications
    (Institute of Electrical and Electronics Engineers Inc., 2024) Ali, T.F.; Dominic D, D.A.; Prabhakaran, P.
    In the realm of medium-power high-volume applications, Switched Reluctance Motor (SRM) drives hold great advantages over other motors. However, the SRM drive must be optimized to reduce cost without compromising the performance for medium power applications. This paper presents a novel SRM drive utilizing a Miller converter-fed SRM motor with a single current sensor, offering a comprehensive control development procedure encompassing system modeling, design procedures, dynamic simulation, analysis, and experimental validation. The SRM is characterized through finite element analysis (FEA) to derive a MATLAB Simulink simulation model, and the conduction angle is optimized for drive efficiency through parametric simulation studies. The linear SRM model for control design is obtained via small signal analysis. Speed and current controllers are designed using the K-factor method, and the efficacy of the proposed drive is rigorously evaluated across various operating modes in MATLAB Simulink. Additionally, a hardware prototype is developed and the digital control algorithm is implemented on the DSP microcontroller TMS320F28379D based on the designed controllers to further assess drive performance. The results obtained validate the robustness and dynamic performance of the SRM drive across variable speed, variable torque, and constant power modes of operation. © 2013 IEEE.