Faculty Publications
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Publications by NITK Faculty
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Item Implementation of comprehensive address generator for digital signal processor(2013) Ramesh Kini, R.M.; Sumam David, S.The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log 2 N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size. © 2013 Copyright Taylor and Francis Group, LLC.Item Energy- and Reliability-Aware Provisioning of Parallelized Service Function Chains With Delay Guarantees(Institute of Electrical and Electronics Engineers Inc., 2024) Chintapalli, V.R.; Killi, B.R.; Partani, R.; Tamma, B.R.; Siva Ram Murthy, C.Network Functions Virtualization (NFV) leverages virtualization and cloud computing technologies to make networks more flexible, manageable, and scalable. Instead of using traditional hardware middleboxes, NFV uses more flexible Virtual Network Functions (VNFs) running on commodity servers. One of the key challenges in NFV is to ensure strict reliability and low latency while also improving energy efficiency. Any software or hardware failures in an NFV environment can disrupt the service provided by a chain of VNFs, known as a Service Function Chain (SFC), resulting in significant data loss, delays, and wasted resources. Due to the sequential nature of SFC, latency increases linearly with the number of VNFs. To address this issue, researchers have proposed parallelized SFC or VNF parallelization, which allows multiple independent VNFs in an SFC to run in parallel. In this work, we propose a method to solve the parallelized SFC deployment problem as an Integer Linear Program (ILP) that minimizes energy consumption while ensuring reliability and delay constraints. Since the problem is NP-hard, we also propose a heuristic scheme named ERASE that determines the placement of VNFs and routes traffic through them in a way that minimizes energy consumption while meeting capacity, reliability, and delay requirements. The effectiveness of ERASE is evaluated through extensive simulations and it is shown to perform better than benchmark schemes in terms of total energy consumption and reliability achieved. © 2017 IEEE.