Faculty Publications
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Item Accurate Performance Analysis of 3D Mesh Network on Chip Architectures(Institute of Electrical and Electronics Engineers Inc., 2018) Halavar, B.; Talawar, B.With the increase in number and complexity of cores and components in CMPs and SoCs, a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network on Chips(NoC) emerged as the reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. In this paper, we explore the design space of 3D NoCs using floorplan driven wire lengths and link delay estimation. We analyse the performance and cost of 2D and two 3D variants of the Mesh topology by injecting two synthetic traffic pattern for varying buffer space and floorplan based delays were considered to for the experiments. Results of our experiments show that for the injection rates from 0.02 to 0.2 the average network latency of a 4layer 3D Mesh is reduced up to 54% compared to its 2D counterpart. The on chip communication performance improved up to 2.2× and 3.1× in 4-layer 3D Mesh compare to 2D Mesh with uniform and transpose traffic patterns respectively. © 2018 IEEE.Item OP3DBFT: A power and performance optimal 3D BFT NoC architecture(Springer Verlag service@springer.de, 2020) Halavar, B.; Talawar, B.Network on Chips (NoC) have emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. The use of 3D IC technology in NoC promises to improve communication latency and power. Most of the 3D ICs use Through-silicon via (TSVs) as vertical interconnect. In this paper, we explore the design space of 2-layer 3D Butterfly Fat Tree (BFT) variants. Floorplan driven wire and TSV lengths are used to obtained power and performance optimal 3D NoC architectures. We analysed the performance of the output flow control using random and round robin output based deflection routing for 3D BFT variants. TSV based power and delay models were extended to a cycle accurate simulator to estimate accurate power and performance of 3D NoC architecture. We propose a new OP3DBFT (Optimal Power and Performance 3DBFT) architecture with round-robin deflection routing (RROD) as power and performance optimal 2-layer 3D NoC architecture. OP3DBFT has symmetric link lengths and 75% of TSVs count reduced compared to the regular 2-layer 3D BFT topology. Results of our experiments show that the performance improved up to 1.39× and 1.3× in OP3DBFT with fewer TSV counts compared to the regular 2-layer 3D BFT for uniform and transpose traffic respectively. The OP3DBFT NoC architecture EDP (Energy delay product) was lower by 40% for uniform traffic and 48% for transpose traffic. © Springer Nature Switzerland AG 2020.