Faculty Publications
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Item Simplified transformer-based multilevel inverter topology and generalisations for renewable energy applications(Institution of Engineering and Technology journals@theiet.org, 2018) Behara, S.; Sandeep, N.; Yaragatti, U.R.Multilevel inverters (MLIs) generating high-quality voltage waveforms are playing a significant role in renewable energy applications. However, the requirement of higher number of power devices, complex pulse-width-modulation (PWM) and voltage unbalancing issues are the impediments associated with their direct usage. Consequently, several attempts to devise MLIs with lesser number of overall components are witnessed. This study focuses on developing a nine-level inverter comprising of a single transformer and reduced component count. An optimisation of the number of transformers and their turn's ratio for a given number of voltage levels resulting in the least number of switches is investigated and deliberated in detail. Besides, an uncomplicated logic gate-based PWM strategy is developed for generating the gating signals of switches using simple Boolean logic relations. A detailed comparison with other recommended MLI topologies is presented to highlight the notable features of the proposed topology. Simulation results obtained using the model developed in MATLAB/Simulink along with the experimental measurements obtained from a downscale prototype is presented to validate the practicability, effectiveness, and viability of the proposed topology. An explicit agreement among the simulation and experimental results is observed. © The Institution of Engineering and Technology 2017.Item Operation and Control of a Nine-Level Modified ANPC Inverter Topology with Reduced Part Count for Grid-Connected Applications(Institute of Electrical and Electronics Engineers Inc., 2018) Sandeep, N.; Yaragatti, U.R.This paper presents a nine-level active-neutral-point-clamped (ANPC) based multilevel inverter (MLI) topology for grid-connected applications requiring only ten switches. The envisaged structure comprises two parts, namely five-level ANPC unit, and a two-level converter leg whose midpoint is used as another ac terminal. An ad hoc switching state redundancy based modulation strategy is used to ensure that the voltage across the flying capacitor is tightly balanced and is implemented using a look-up table further simplifies the control complexity. The performance and effectiveness of the proposed topology with its control scheme are validated through simulations and experimental tests. Comparison with other MLIs is included to highlight the merits of the proposed topology. From the results, it will be shown that the proposed inverter requires the least part count as compared to other topologies with the same performance and output quality. © 1982-2012 IEEE.Item A Switched-Capacitor-Based Multilevel Inverter Topology with Reduced Components(Institute of Electrical and Electronics Engineers Inc., 2018) Sandeep, N.; Yaragatti, U.R.This letter presents an improved sensorless nine-level inverter topology with reduced number of components. It is formed by cascading a three-level T-Type neutral clamped point inverter with a floating capacitor (FC) fed two-level converter unit. Additionally, two line-frequency switches are appended across the dc-link. A simple logic-form equations-based pulse width modulator is designed which is in-charge of maintaining the FC voltage at its reference value without any aid of voltage and current sensor. Thus, the complexity in control of the proposed topology is very minimal. The working principle of the proposed inverter and formulation of logic-form equations is deliberated in detail. Furthermore, experimental results obtained from the developed prototype are presented to validate feasibility and operability of the proposed topology. Finally, a comprehensive comparison with some of the recently reported inverter topologies proving the merits of the proposed topology is included. © 1986-2012 IEEE.Item Design and Implementation of Transformer-Based Multilevel Inverter Topology with Reduced Components(Institute of Electrical and Electronics Engineers Inc., 2018) Behara, S.; Sandeep, N.; Yaragatti, U.R.This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. © 1972-2012 IEEE.Item A Self-Balancing Five-Level Boosting Inverter with Reduced Components(Institute of Electrical and Electronics Engineers Inc., 2019) Sandeep, N.; Jagabar Sathik, J.S.; Yaragatti, U.R.; Krishnasamy, K.Two-Stage boosting multilevel inverters (MLIs), which are highly suitable for photovoltaic power plants, are known to suffer because of the high voltage stress on the switches of second stage. One of the ways to confront this issue is through eliminating the front-end booster. However, this leads to increased structural and control complexity of the resulting integrated boosting MLI. This letter presents a single-stage boosting MLI requiring lesser number of switches, diodes, and capacitors for renewable power generation applications. It requires nine switches and only one capacitor for five-level voltage generation. The topology has inherent self-balancing capability, thereby does not need additional balancing circuitry. The proposed topology has a uniform peak inverse voltage stress on the switches of value equal to the input dc voltage. A less complicated logic-form-equations-based gating pulse generation scheme is designed for enabling the proposed MLI to maintain its capacitor voltage. Further, a comparative study with state-of-the-art topologies is carried out to demonstrate the superior performance of the proposed topology. Finally, the feasibility of the proposed topology is validated through experimental tests and the corresponding results are elucidated. © 1986-2012 IEEE.