Faculty Publications

Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736

Publications by NITK Faculty

Browse

Filters

20182

Settings

Author: search.filters.author.Yaragatti, U.R.Subject: search.filters.subject.Design and implementations

Search Results

Now showing 1 - 2 of 2
  • No Thumbnail Available
    Item
    Design and implementation of active neutralpoint-clamped nine-level reduced device count inverter: An application to grid integrated renewable energy sources
    (Institution of Engineering and Technology journals@theiet.org, 2018) Sandeep, N.; Yaragatti, U.R.
    Multilevel inverters are one of the preferred choices in medium-voltage and high-power applications in the recent past. Active neutral-point-clamped (ANPC) inverter is the most popular topology, especially in the class of five-level (5L) inverters. In this study, a nine-level topology with improved output waveform quality is proposed based on ameliorating the 5L ANPC inverter with least modifications. The addition of only two switches operating at line frequency to the conventional 5L ANPC inverter while maintaining an identical precursor part count is the proposed modification. A logic form equation-based active voltage balancing scheme that is independent of load current and power factor is developed to regulate the flying capacitor voltage at the reference value. The operating principle, salient features, and the developed control scheme are comprehensively detailed. The operation of the proposed inverter considering a grid integrated case is simulated in MATLAB/ Simulink, and the results corresponding to steady-state and dynamic conditions are presented. The benefits of the proposed topology are elucidated by comparing it with other classic topologies considering various prominent viewpoints. This comparison has illustrated the proposed topology's distinctive characteristics and profound advantages. The performance validation, feasibility, and practicability of the proposed inverter are established through the experimental results obtained from a laboratory-scale prototype. © The Institution of Engineering and Technology 2017.
  • No Thumbnail Available
    Item
    Design and Implementation of Transformer-Based Multilevel Inverter Topology with Reduced Components
    (Institute of Electrical and Electronics Engineers Inc., 2018) Behara, S.; Sandeep, N.; Yaragatti, U.R.
    This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. © 1972-2012 IEEE.