Faculty Publications
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Item A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line(Institute of Electrical and Electronics Engineers Inc., 2022) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author's best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band's drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP1dB OP1dB), third-order input output intercept point (IIP3 OIP3) of -17/-16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61 $\times $ 0.92 mm2. © 2013 IEEE.Item A 0.15 μm GaN HEMT device to circuit approach towards dual-band ultra-low noise amplifier using defected ground bias technique(Elsevier GmbH, 2023) Gupta, M.P.; Kumar, S.; Elizabeth Caroline, B.; Song, H.; Kumar, V.; Gorre, P.This work presents a GaN HEMT device to circuit approach towards low noise amplifier (LNA) using defective ground bias (DGB) technique. This is the first MMIC GaN HEMT LNA design to offer dual-band of operation in both L and S-bands to the author's best knowledge. The proposed 0.15-μm GaN HEMT device fabrication achieves a high output power of 20 W using slot radiation phenomenon. The proposed DGB technique consists of gate and drain biasing topologies which achieves a dual-band of operation using microwave approach. The DGB technique is incorporated into GaN HEMT LNA which achieves high input and output power with good stability. To achieve an optimal noise, high I/O power, and almost flat gain at both L and S-bands, the defective ground structure of bias topologies is modeled and optimized. An artificial ground defect is created to offer resonant properties for the DGS of a microstrip line, which utilizes frequency-selective properties to improve the performance of the LNA circuit by suppressing the harmonics and scaling the size. The dedicated LNA shows the benefits of compact size, extremely low noise figure of 0.74/1.6 dB, high output power of 44 dBm and nearly flat gain of 14/11 dB at 1.17/2.49 GHz with the unique methodologies suggested. The compact GaN HEMT LNA could overcome the weak signal strength received by RF receiver for smart rail transport system. © 2023 Elsevier GmbHItem A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems(Elsevier GmbH, 2024) Naik, D.N.; Gorre, P.; Prasad Gupta, M.; Kumar, S.; Al-Shidaifat, A.; Song, H.In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V. © 2023Item Performance Analysis of Novel Graphene Process Low-Noise Amplifier with Multi-stage Stagger-Tuned Approach over D-band(Springer, 2024) Nandini, P.; Naik, D.N.; Gorre, P.; Gupta, M.P.; Kumar, S.; Al-Shidaifat, A.; Song, H.This work reports an ultra-low noise, multi-stage stagger-tuned low-noise amplifier (MS-ST-LNA) over the D-band performance and achieves a best trade-off between noise, bandwidth, and gain parameters. The ultra-low-noise is achieved in three ways: First, the high-gain 3-stage stagger tuned amplifier (STA) realizes a 3X gain compared to the conventional single-stage amplifier, which sets a low floor noise. Second, the stagger-tuned amplifier achieves 1.6 times lower noise than the traditional single-stage amplifier. Finally, the stagger tune realizes a high-order transfer function, which mitigates the high-frequency noise. The full LNA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using a 0.065-?m commercial process, occupying an area of 0.21 mm2. The proposed design achieves an optimum performance: a maximum measured gain of 20.5 dB and a minimum noise figure (NF) of 4.2 dB over 123.7 to 162.5 GHz. The proposed LNA consumes ultra-low power consumption of 21.3 mW under the power supply of 1.2 V. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.