Faculty Publications
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Item Investigation of CMOS Based Integration Approach Using DAI Technique for Next Generation Wireless Networks(Springer New York LLC barbara.b.bertram@gsk.com, 2019) Roy, G.M.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.This research work investigates a CMOS based low noise amplifier (LNA) using differential active inductor with eight-shaped patch antenna for next generation wireless communication. The proposed work conceded into three different phases. The first phase proposes LNA architecture which includes multistage cascode amplifier with a gate inductor gain peaking technique. The ground approach for this architecture employs active inductor technique that includes two stages of differential amplifier. The proposed novel technique leads to give incremental in inductance by using of common mode feedback resistor and lowers the undesirable parasitic resistance effect. Additionally, this technique offers gain enhanced noise cancellation and achieves a frequency band of around 5.7 GHz. The proposed architecture includes single stage differential AI and enhances the bandwidth up to 6.8 GHz with peak gain of 21 dB at 7.8 GHz. The noise figure and stability factor are achieved which is reasonably good at 1 dB. The proposed architecture is design and optimized on advanced design RF simulator using 0.045 µm CMOS process technology. While in second phase, a narrow band eight-shaped patch antenna is designed which provides operating band range from 5.8 to 6.5 GHz with 6.2 GHz resonating frequency. Highest peak gain of 15 dB and maximum radiation power of 42.5 dBm is succeed by proposed antenna. The final phase provides integration strategy of LNA with antenna and achieves desired gain of nearly 21 dB with minimum NF of 1.2–1.5 dB in the same band. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.Item Performance of ultra-wide band DCBLNA with suspended strip line radiator for human breast cancer diagnosis medical imaging application(Institution of Engineering and Technology, 2020) Roy, G.M.; Kumar Kanaujia, B.K.; Dwari, S.; Kumar, S.; Song, H.This study presents the performance of differential cascode balun low noise amplifier (DCBLNA) with ultra-wideband (UWB) for human breast cancer diagnosis. The proposed DCBLNA design-I with bulky spiral inductors achieves insufficient bandwidth with large power consumption of 10.8 mW. To attain the proper UWB band of operation, suspended strip line (SSLIN) radiators have employed in the proposed design-I. The performance of SSLIN is evaluated in terms of line capacitance and characteristic impedance by optimising its width. It is observed that best 50 ?n-II. DCBLNA design-II using SSLIN have achieving a desired band of operation ranging from 1.5 to 15.7 GHz and best NF of 0.5 dB. The gain and phase imperfections are simulated to characterise balun networks. The smallest gain imperfection achieved is 0.1 dB at 10 GHz while the simulated phase imperfection turns out to be sufficiently good with 2.35° at 8 GHz. The proposed DCBLNA design-II is implemented and fabricated using RFCMOS 45 nm Taiwan Semiconductor Manufacturing Company (TSMC) process under commercial conditions. The highest figure of merit comes out to be 3.2 that ensures good accuracy of medical imaging for breast cancer diagnosis. © The Institution of Engineering and Technology 2020.Item Performance analysis of 65 nm CMOS LNA using SSL technique for 5G cellular front-end receivers(Elsevier GmbH k.ernst@elsevier.com, 2020) R, V.; Gorre, P.; Song, H.; Kumar, S.This paper presents a performance analysis of a wideband low noise amplifier (LNA) that utilizes a 65 nm CMOS Samsung mm-wave process. The proposed CMOS LNA designed with new built-in techniques will overcome the challenges faced by device parasitic and electromagnetic (EM) losses. A suspended substrate line (SSL) is characterized and analyzed with its dual-band operation and achieves excellent EM compatibility. The traditional EM losses in bulk active and passive components have been incurred using built-in techniques to provide better linearity of LNA. The proposed mm-wave LNA enables it's each family component to avoid leakage of EM waves and its interconnected parasitic losses in layout. An SSL based parallel-series network is optimized to achieve a wide bandwidth of 26 GHz to 34 GHz. The full design of LNA achieves the highest peak gain of 25 dB by using proper 50 ? matching constraints over the wideband response of 27.8 GHz to 32.5 GHz. The fabricated chip of LNA is given a supply voltage of 1.2 V, and the calculated chip area is 0.35*0.22 mm2. The simulation and measurement results demonstrate the minimum noise figure of 2.5 dB and achieve the highest stability factor in the desired band of operation. The LNA also measured linearity with a 1 dB compression point where input power of ?19dBm has obtained at 30.5 GHz. © 2020 Elsevier GmbHItem Active feedback supported CMOS LNA blended with coplanar waveguide-fed antenna for Wi-Fi networks(John Wiley and Sons Inc, 2021) Roy, G.M.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi-Fi networks. The LNA design-I, involves a cascode amplifier followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor-less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design-II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign-III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost. © 2021 The Authors. IET Microwaves, Antennas & Propagation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.Item Highly robust X-band quasi circulator-integrated low-noise amplifier for high survivability of radio frequency front-end systems(John Wiley and Sons Ltd, 2021) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.In this brief, an X-band quasi circulator (QC)-integrated low-noise amplifier (LNA) implemented in 65-nm Complementary Metal Oxide Semiconductor (CMOS) technology is presented. This work is the first QC-LNA for the X-band to the author's best knowledge, which achieves 30-dB flat gain in 8–12 GHz with only 0.5-dB variation across the band. This QC-LNA uses two-stage current reused techniques with variable impedance load. QC provides the minimum insertion loss of 0.9 dB with good return and isolation losses. Statistical analysis is presented for QC-LNA to predict the percentage error tolerance. Quasi-Newton (QN) control algorithm is used to optimize the parameter of the whole design. The design of experiment (DoE) is performed to claim the contribution towards gain, return loss, and noise figure. The proposed LNA measurement provides a minimum NF of 1 dB at 9.5 GHz, which remains less than 1.4 dB across 8–12 GHz. The fabricated LNA works with a supply voltage of 1.2 V and is unconditionally stable across the frequency. The calculated chip area is 0.84 × 0.52 mm2. This QC-LNA exhibits an input and output 1-dB compression point (IP1dB and OP1dB) of ?15 and +13.8 dBm, respectively. It also exhibits third-order input and output intercept point (IIP3 and OIP3) of +10 dBm and of +40 dBm, respectively. The proposed QC-LNA draws only 8.7 mA from 1.2 V. © 2021 John Wiley & Sons, Ltd.Item A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line(Institute of Electrical and Electronics Engineers Inc., 2022) Vignesh, R.; Gorre, P.; Song, H.; Kumar, S.This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author's best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band's drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP1dB OP1dB), third-order input output intercept point (IIP3 OIP3) of -17/-16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61 $\times $ 0.92 mm2. © 2013 IEEE.Item A 0.15 μm GaN HEMT device to circuit approach towards dual-band ultra-low noise amplifier using defected ground bias technique(Elsevier GmbH, 2023) Gupta, M.P.; Kumar, S.; Elizabeth Caroline, B.; Song, H.; Kumar, V.; Gorre, P.This work presents a GaN HEMT device to circuit approach towards low noise amplifier (LNA) using defective ground bias (DGB) technique. This is the first MMIC GaN HEMT LNA design to offer dual-band of operation in both L and S-bands to the author's best knowledge. The proposed 0.15-μm GaN HEMT device fabrication achieves a high output power of 20 W using slot radiation phenomenon. The proposed DGB technique consists of gate and drain biasing topologies which achieves a dual-band of operation using microwave approach. The DGB technique is incorporated into GaN HEMT LNA which achieves high input and output power with good stability. To achieve an optimal noise, high I/O power, and almost flat gain at both L and S-bands, the defective ground structure of bias topologies is modeled and optimized. An artificial ground defect is created to offer resonant properties for the DGS of a microstrip line, which utilizes frequency-selective properties to improve the performance of the LNA circuit by suppressing the harmonics and scaling the size. The dedicated LNA shows the benefits of compact size, extremely low noise figure of 0.74/1.6 dB, high output power of 44 dBm and nearly flat gain of 14/11 dB at 1.17/2.49 GHz with the unique methodologies suggested. The compact GaN HEMT LNA could overcome the weak signal strength received by RF receiver for smart rail transport system. © 2023 Elsevier GmbHItem A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems(Elsevier GmbH, 2024) Naik, D.N.; Gorre, P.; Prasad Gupta, M.; Kumar, S.; Al-Shidaifat, A.; Song, H.In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V. © 2023Item Performance Analysis of Novel Graphene Process Low-Noise Amplifier with Multi-stage Stagger-Tuned Approach over D-band(Springer, 2024) Nandini, P.; Naik, D.N.; Gorre, P.; Gupta, M.P.; Kumar, S.; Al-Shidaifat, A.; Song, H.This work reports an ultra-low noise, multi-stage stagger-tuned low-noise amplifier (MS-ST-LNA) over the D-band performance and achieves a best trade-off between noise, bandwidth, and gain parameters. The ultra-low-noise is achieved in three ways: First, the high-gain 3-stage stagger tuned amplifier (STA) realizes a 3X gain compared to the conventional single-stage amplifier, which sets a low floor noise. Second, the stagger-tuned amplifier achieves 1.6 times lower noise than the traditional single-stage amplifier. Finally, the stagger tune realizes a high-order transfer function, which mitigates the high-frequency noise. The full LNA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using a 0.065-?m commercial process, occupying an area of 0.21 mm2. The proposed design achieves an optimum performance: a maximum measured gain of 20.5 dB and a minimum noise figure (NF) of 4.2 dB over 123.7 to 162.5 GHz. The proposed LNA consumes ultra-low power consumption of 21.3 mW under the power supply of 1.2 V. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.