Faculty Publications
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Item An integrated cascode DE power amplifier for RF calibration system towards measurement of bio-sensor applications(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2019) Kumar, R.; Kumar Kanaujia, B.K.; Dwari, S.; Kumar, S.; Song, H.The integrated cascode DE power amplifier for RF calibration system toward measurement of bio-sensor applications is presented in this paper. The proposed architecture includes cascode class-D and class-E amplifier stages that could provide better calibration accuracy in terms of wide bandwidth, power efficiency, high gain, minimum group delay, and lowest calibration system. The achieved high performance of proposed amplifier overcomes conventional measurement issues toward bio-sensor application. The inductive ?-shape matching network drives RF input to class-D stage and provides wide bandwidth of operation. While class-E stage with T-shape matching network maintains stable gain and high efficiency in desired band of operation. The performance of the CMOS proposed amplifier is executed in RF ADS simulator along with fabricated chip using commercial TSMC 65 nm manufacturing process. The simulated and measured data achieves Ku band (12 GHz to 18 GHz) with almost flat gain of 30 dB. The DE amplifier provides an output and saturated power of 17 dBm with highest power efficiency of 45%. The measured calibration factor at maximum resonant frequency of 13.5 GHz achieves best value of less than 2 dB within input power range of ?50 dBm to 0 dBm. The lowest calibration factor provides best accuracy along with the other parameters and could be beneficial toward bio-sensor measurement in the various applications. The calculated area of the fabricated chip is as 0.45*0.45mm2 where class-E consuming area of 38% and class-D of 44%. The fabricated chip consumes less power consumption of 3.2 mW under power supply of 1 V. © 2018 Wiley Periodicals, Inc.Item Reconfigurable Wide Bandwidth Using Novel Extraction Technique of Slotted Monopole Antenna with RF CNT Network(Springer New York LLC barbara.b.bertram@gsk.com, 2019) Kumar, S.; Song, H.; Kanuajia, B.K.This work first moment focuses on the concept of reconfigurable wide bandwidth using novel extraction technique of slotted monopole antenna with RF carbon nanotube (CNT) network. The entire approach is folded into four different designs. The first design proposes a monopole antenna where asymmetric flower type corners and mushroom shape encloses by T-slot is cut on the patch. This new shaped antenna covers wide impedance bandwidth of about 14.5 GHz within range from 21.5 to 36 GHz. The proposed antenna observed that lower bands are excited with new resonating modes by inserting T-slot upon mushroom shape while higher bands are effected due to asymmetric flower type corners on the patch. A wide range of gain from 16.3 to 20.5 dB with maximum axial ratio bandwidth of 2.8% is also succeed. Measured and simulation results for proposed antenna shows good agreement with each other. In second design, a novel extraction technique is used for equivalent model of slotted monopole antenna which shows promising agreement with the original geometry. Thirdly, introduces RF CNT equivalent model which demonstrates its ability to resonant at wideband within range of 12.4–25.1 GHz with 68% of fractional impedance bandwidth. Finally, RF equivalent model of slotted monopole antenna is integrated with CNT for the proper operation. The fabrication of integration network scenario proves notability of reconfiguration in aspect of wide bandwidth with the compactness. A frequency switchable notability dominant some excited additional resonant modes using proper impedance matching between proposed antenna and RF CNT. This proposed work is fascinating to our integration network which fully covered K-band and almost for Ka-band application. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.Item Performance of cascode Class-EF?1 PA with built-in techniques for UWB radar toward monitoring of patient actions(Institution of Engineering and Technology kvukmirovic@theiet.org, 2020) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This work proposes a performance of the cascode Class-EF?1 power amplifier (PA) for UWB radar transmitter. The cascode Class-E PA with built-in techniques overcomes the traditional mismatch and provides good performance of PA. Incurs the resonance and switching effect is observed in cascode Class-E PA that compensates for the parasitic effects and provides a wide-impedance range. While design-II includes negative capacitance and inverse Class-F, which achieves a redundant performance of wide bandwidth and power-added efficiency (PAE). Design-II achieves the redundant performance compared with design-I. Both design-I and design-II are implemented and analysed through simulation and experimental results using RF 65 nm Samsung Magnachip Hynix CMOS process. Design-I achieves a wide-impedance bandwidth ranging from 3 to 11.7 GHz with drain efficiency (DE) and maximum PAE of 80 and 73% at the output power of 26.4 dBm. The global efficiency (GE) and error vector magnitude (EVM) of 70 and 5.2% are also achieving for design-I. The redundant performance in design-II achieves wide bandwidth with operating frequency range of 2-13 GHz with maximum DE and PAE of 85 and 76%. For design-II, GE and EVM are investigated as 68 and 4.9% that could validate the accuracy and robustness of the UWB radar. © The Institution of Engineering and Technology 2019Item A 61.2-dB?, 100 Gb/s Ultra-Low Noise Graphene TIA over D-Band Performance for 5G Optical Front-End Receiver(Springer, 2021) Gorre, P.; Vignesh, R.; Song, H.; Kumar, S.This work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-?m process. The TIA achieves a flat transimpedance gain of 61.2 dB? with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/?Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10?12 is achieved. The chip occupies an area of 0.92 * 1.34 mm2 while consuming power of 21 mW under supply of 1.8 V. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.Item Active feedback supported CMOS LNA blended with coplanar waveguide-fed antenna for Wi-Fi networks(John Wiley and Sons Inc, 2021) Roy, G.M.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi-Fi networks. The LNA design-I, involves a cascode amplifier followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor-less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design-II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign-III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost. © 2021 The Authors. IET Microwaves, Antennas & Propagation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.Item A 64 ?dB?, 25 ?Gb/s GFET based transimpedance amplifier with UWB resonator for optical radar detection in medical applications(Elsevier Ltd, 2021) Gorre, P.; Vignesh, R.; Song, H.; Kumar, S.This work reports a novel Graphene Field Effect Transistor (GFET) based transimpedance amplifier (TIA) for optical radar detection in medical applications. Design-I includes a microstrip line (MSL) based UWB resonator circuit which enables the TIA design to operate in UWB range of frequency with high Q-factor. Design-II comprises MSL UWB resonator integrated stagger-tuned CR-RGC TIA which enhances the transimpedance limit and mitigates the effect of photodiode capacitance results in higher bandwidth performance. The proposed TIA realizes a 2.6 times lesser noise compared to the conventional CR-RGC TIA. A flat transimpedance gain of 64 ?dB? and ultra-low input-referred noise current density of 8.9 pA/?Hz are achieved using gain and noise optimization methods. Additionally, a dynamic range of 49 ?dB with a group delay variation (GDV) of ±25 ps is achieved over the entire UWB range. The TIA demonstrates a 25 ?Gb/s data rate while a bit-error-rate (BER) less than 10?10 is achieved. The chip occupies an area of 0.67?0.72 ?mm2 while consuming power of 19 ?mW under the supply voltage of 1.8 ?V. © 2021 Elsevier LtdItem A 8–12 GHz, 44.3 dBm RF output class FF?1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters(Springer, 2021) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This paper presents a high-efficiency Class FF - 1 DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.Item A 2.71-pA/√Hz ultra-low noise, 70-dB dynamic range CMOS transimpedance amplifier with incorporated microstrip line techniques over extended bandwidth(John Wiley and Sons Ltd, 2023) Gorre, P.; Vignesh, R.; Kumar, S.; Song, H.; Roy, G.M.Recent advancements in the area of telemedicine have focused on remote patient monitoring services as a new frontier in medical applications. The present work reports a 65-nm complementary metal–oxide–semiconductor (CMOS)-based transimpedance amplifier (TIA) in an optical radar system for non-contact patient monitoring. A T-shaped microstrip line (MSL) integrated with variable gain common source TIA using MSL peaking technique and off-chip post-amplification integration is a newly proposed architecture to achieve a ultra-low noise, high dynamic range (DR) and high figure of merit over broadband than a traditional TIAs. First, the integrated T-shaped MSL develops an additional resonant frequency that resonates with a photodiode capacitance improving the bandwidth performance at higher Q values. Second, the shunt MSL peaking technique that introduces an additional conjugate pole-pair that cancels the effect of input capacitance helps to further improve the bandwidth of the TIA. Finally, an active feedback concept achieves a wide linear dynamic range enabling high TIA detectability. The proposed TIA realizes an impedance bandwidth of 770 MHz ranging from 7.12 to 7.89 GHz with a transimpedance gain of 105.1 dBΩ and ultra-low input-referred noise (IRN) density of 2.71 pA/√Hz. A high linear DR of 70 dB is achieved by employing a variable gain control scheme with a low group delay variation of 0.81 ns. The proposed work demonstrates a 1-Gb/s data rate while a bit-error rate less than 10−12 is achieved. The TIA consumes a power of 0.82 mW under the supply voltage of 1.2 V. © 2022 John Wiley & Sons Ltd.Item A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems(Elsevier GmbH, 2024) Naik, D.N.; Gorre, P.; Prasad Gupta, M.; Kumar, S.; Al-Shidaifat, A.; Song, H.In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V. © 2023