Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
37 results
Search Results
Item Mm-wave cmos power amplifiers for 5g(Springer Science and Business Media Deutschland GmbH, 2021) Gorre, P.; Kumar, R.; Song, H.; Kumar, S.The chapter discusses the basic elements in the design of mm-wave CMOS Power Amplifier (PA) for phased arrays integration, focusing the next-generation 5G mobile communication. Power Amplifier design metrics, along with implementation of beam-forming phased arrays to merge power over-the-air are discussed in brief. The explanation begins with CMOS unique advantages, real-time handset challenges, system-level constraints, and design challenges are conceptually demonstrated with the help of a basic single-stage transistor Power Amplifier. © Springer Nature Singapore Pte Ltd. 2021.Item Techniques to improve gain-bandwidth 5g ics(Springer Science and Business Media Deutschland GmbH, 2021) Vignesh, R.; Kumar, R.; Song, H.; Kumar, S.This chapter introduces a basics of designs and techniques to improve gain-bandwidth for 5G ICs. The major focus would be on the various network topologies that yield to provide easy implementation of on-chip components for 5G-ICs. Section 1 discusses the basics of RLC tank networks, which includes RC parallel network, RLC network and series to parallel resonant network. The parameters such as quality factor, noise of filter networks are shortly refresh while foundation of resonant circuits would set-up for 5G transceiver ICs. Section 2 introduces coupled resonator networks can be used as microwave components to achieve a better gain-bandwidth trade-off. Finally, Sect. 3 will provide transformer resonators and circuit to reduce bulky components and enhance gain-bandwidth of ICs. © Springer Nature Singapore Pte Ltd. 2021.Item A 28-32GHz CMOS LNA with broadband approach for 5G Mm-wave communication cells(Institute of Electrical and Electronics Engineers Inc., 2019) Vignesh, R.; Gorre, P.; Kumar, S.; Song, H.This paper first time reports a wideband low noise amplifier (LNA) with achievable minimum atmospheric absorption frequency band for 5G millimeter wave communication cells. A novel suspended substrate line based parallel-series network is optimized and analyzed that demonstrates a wideband response. The proposed LNA consists of two stage Cascode topology with incorporated parallel-series network and microwave components that provides broadband ranging from 28GHz to 32GHz. A full of two stage Cascode LNA overcoming the traditional mismatching constraints with consideration of suspended substrate lines (SSL) and Tee-junction in the proposed design. It is observed that suspended lines reduce parasitic and bulk effects of devices and enables LNA to provide broadband communication for 5G macro and micro cells. The proposed design is realized using RF 65nm Magna Hynix CMOS process with layout cell. The simulation results reveals that 28GHz-32GHz wide band with maximum forward gain of 25dB. The minimum noise figure of 2.5dB is achieved with optimization of passive components. The input impedance (real and imaginary) and smith chart realization for LNA provides satisfactory performance. © 2019 IEEE.Item A 73% PAE, Highly Gain Inverse Class-F Power Amplifier for S-Band Applications(Springer Science and Business Media Deutschland GmbH, 2021) Naik, J.D.; Gorre, P.; Kumar, R.; Kumar, S.; Song, H.This paper proposes a continuous-mode inverse Class F power amplifier (PA) achieving wide bandwidth, high output power, and high efficiency. This work includes transmission line-based output/input matching networks and single-ended topology. The main focus of the work is to achieve a high gain with wide bandwidth. The proposed structure incorporates a termination of even and odd harmonics to deliver voltage and current waveform isolation with minimal matching network (MN) design complexities. The analyses simulated in Keysight Technologies Advanced Design System (ADS), which results in a wideband PA design. The results are quantified by using high power-added efficiency (PAE) and output power. PAE of 72.6% and output power more than 41 dBm obtained over wide bandwidth 2–4.2 GHz at −3 dB gain compression. The proposed PA could overcome the traditional performance and utilize for green communication. © 2021, Springer Nature Singapore Pte Ltd.Item Logic Gates Using Memristor-Aided Logic for Neuromorphic Applications(Springer Science and Business Media Deutschland GmbH, 2023) Khan, S.R.; Haque, M.N.; Islam, M.T.; Naik, J.D.; Al-Shidaifat, A.D.; Song, H.; Kumar, S.Data transfer rate has been a hornets’ nest for modern systems memory and CPU. One of the more appealing potentials to overcome the limits is to combine memory and processing at the same site where the data is stored. Memory processing has been exhibited using memristor-aided logic (MAGIC) operations in memristor. In this paper, Ag/AgInSbTe/Ta (AIST)-based memristor has been used to implement the memristor-based logic design. A memristor-only logic family referred to as MAGIC technique is used to perform logic gates such as AND, OR, NOT, and NAND. The logical operations were executed using Verilog-A model, and the figures of those operations are shown. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.Item A High-Sensitive High-Input Impedance CMOS Front-End Amplifier for Neural Spike Detection(Springer Science and Business Media Deutschland GmbH, 2023) Naik, J.D.; Gorre, P.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.Neural spikes detection and monitoring for neuro-prosthetic applications require an efficient and robust front-end amplifier (FEA), which regulates the fidelity of the neural signal. This paper presents neutralization and bootstrapping techniques to overcome the input leakage currents produced by amplifiers of the input bias network. In addition, a pseudo-resistor technique ensures the FEA maintains a high-input impedance. The CMOS-based FEA architecture is executed in the advanced design system with the design kit of the CMOS process. The proposed design achieves a high-input impedance of 0.5 TΩ with a maximum simulation gain of 66.2 dB. The overall power consumption of the topology is observed as 2.6 µW with a power supply voltage of 0.9 V. The simulated noise performance of 6 nV/√Hz at 1 kHz demonstrates a high-sensitive design compared to the previous works. It is highly recommended for succeeding neuro-prosthetic applications. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.Item A Low-Power Highly Efficient DC–DC Buck Converter Using PWM Technique(Springer Science and Business Media Deutschland GmbH, 2023) Islam, M.T.; Haque, M.N.; Khan, S.R.; Naik, J.D.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.Integrated digital circuits (IDCs) have become a popular option for DC–DC buck converters. This article describes a novel CMOS DC–DC buck converter architecture that leverages pulse-width modulation (PWM) for low-power technology. Double delay lines are used in the PWM power consumption which is minimized throughout design and improve unstable voltage while increasing resolution. The functioning of PWM is described using an algorithm developed. Under the working frequency of 100 kHz, the promising findings suggest that the power consumption is reduced to 1.17 W while taking up less space. With a current, the DC–DC buck converter using PWM has a high efficiency of 92.2% across a power range of 4–10 mA. Compared to traditional converters, our PWM approach reduces ripple voltage by 48% and allows in order to create within a DC–DC converter in a smaller chip area. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.Item A Wideband Microstrip Line-Based Balun Structure for High Power Amplifier Applications(Springer Science and Business Media Deutschland GmbH, 2023) Gupta, M.P.; Gorre, P.; Kumar, S.; Song, H.This paper proposes a balun matching technique to achieving a high output power and wide bandwidth. The proposed structure includes microstrip transmission line-based even and odd mode-matching circuits. A three-port unipolar microstrip line is designed to transform the balanced load termination to 50 Ω unbalanced port impedance. The proposed network design is based on real symmetrical four port network with open ended transmission line is inserted between the middle of the structure. To improve the isolation, transmission coefficient parameter and match the 50 Ω termination, a resistive network is inserted between the two balanced ports. The proposed structure is simulated in Keysight Technologies Advanced Design System (ADS), fabrication is done by using 0.51 mm RT Duriod substrate alignments. To verify the design concept, first of all, a wideband microstrip matching technique is designed and characterized at the frequency of L5 band (1.17 GHz). Then a prototype of microstrip transmission line-based wideband balun matching circuit is designed and fabricated. Analytical design equations have been derived for the even mode as well as odd mode techniques which satisfied the results. The proposed balun could overcome power loss mechanism over traditional transmission line structures and can utilize for high power application. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.Item An Ultralow-Power CMOS Integrated and Fire Neuron for Neuromorphic Computing(Springer Science and Business Media Deutschland GmbH, 2023) Haque, M.N.; Khan, S.R.; Islam, M.T.; Naik, J.D.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.Very large-scale integration (VLSI) implementations of spiking neurons are vital for a range of applications, from high-speed modeling of large neural systems to real-time behavioral systems and bidirectional brain-machine interfaces. The circuit solution utilized to implement the silicon neuron is determined by the application’s needs. This paper describes an ultralow-power analog circuit for realizing a leaky integrate and fire neuron model. The suggested circuit comprises parts for executing spike-frequency adaptation and modifying the neuron’s threshold voltage, in addition to being designed for low-power consumption. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.Item A high efficiency on-chip reconfigurable Doherty power amplifier for LTE communication cells(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2018) Kumar, R.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.In this paper, a high efficiency on-chip reconfigurable Doherty power amplifier (DPA) with proposed topology is proposed for LTE or 4G communication cells. The proposed DPA consists of input driver topology, hybrid coupler, asymmetric amplifiers, and 1:1 balun filtered network. The proposed input driver circuit provides wide amplified signal operation within range of 2.3GHz to 6GHz with flat gain of 33 dB. The amplified signal is unsteadily divided into two paths toward the carrier and the power amplifier by 900 hybrid couplers and demonstrates 27.6 dB and 28.3 dB of gain along with 83.2% and 84.5% of power added efficiency at average output power of 40 dBm. The high efficiency and almost flatness in gain stability of proposed DPA providing better solution in order to overcome the interference and the broadband issues for LTE communication cells. The balun-filtered network is employed for combined the two outputs of carrier and peak amplifiers that provides more uniform desired band of operation in the frequency responses. The proposed DPA circuit are implemented and optimized by using advanced design RF simulator platform. The fabricated chip is made by using 0.13 ?m GaN HEMT on Si-Nitride monolithic microwave integrated circuit die process. The fabricated chip of DPA provides 85% of PAE with 28 dB gain which are made close agreement with simulation results. The size of chip is 2.8*1.2mm2 which occupies less die area as compared to existing DPAs. © 2018 Wiley Periodicals, Inc.