Faculty Publications

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    Design and implementation of a symmetrical multilevel inverter topology
    (Institute of Electrical and Electronics Engineers Inc., 2017) Shiva Naik, B.S.; Venkataramanaiah, J.; Reddy, K.S.; Yellasiri, Y.
    In this project level shifted bipolar sinusoidal Pulse Width Modulation techniques are developed over new symmetrical seven level inverter topology. The proposed SPWM techniques are Phase Disposition Technique, Phase Opposition Disposition Technique and Alternate Phase Opposition Disposition Technique which are under hard switching techniques. More number of components, complex switching patterns and charge balance problems are disadvantages of traditional cascaded MLI [1]. In this new topology, reversing voltage component is used in order to reduce the drawbacks mentioned above. So, it possesses fewer components especially in higher level inverters, reduced losses and stress over the components. Proposed techniques are validated on MATLAB-SIMULINK software. Among all the techniques, Phase Opposition disposition technique produced high RMS output voltage with low total harmonic content. © 2017 IEEE.
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    A Single Stage Switched-Capacitor Hexad Boost Multilevel Inverter Featuring Boost Ability
    (Institute of Electrical and Electronics Engineers Inc., 2020) Shiva Naik, B.S.; Yellasiri, Y.; Venkataramanaiah, J.
    Nowadays, curtailment in the number of dc sources, circuit component count along with the boosting gain property of the output voltage are considered as the essential topological features for the new multilevel inverter (MLI) structures. Considering the above, a novel 13-level single-stage switched-capacitor hexad boost (S3 CHB) inverter featuring boosting gain and self-balancing ability is proposed in this paper. Each phase of the proposed \mathrm{S}^{3} CHB-MLI is designed with only 14 semiconductor switches and three electrolytic capacitors. Here, the capacitors' voltages are balanced automatically by utilizing the series-parallel technique effectively. An absence of H-bridge at the back-end makes the circuit to extend for higher levels. Capacitors' voltage ripple are analyzed in detail. Further, a cost comparison is conducted among the state-of-art MLIs to highlight the superiority of the proposed configuration. Finally, the effectiveness of the proposed \mathrm{S}^{3} CHB circuit is experimentally demonstrated. Results at different load conditions are captured to prove the inductive load capability. © 2020 IEEE.
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    A Dual Boost Multilevel Inverter Circuit for Renewable Energy Applications
    (Institute of Electrical and Electronics Engineers Inc., 2020) Bharadwaj, L.; Yellasiri, Y.; Shiva Naik, B.S.; Nageswar Rao, B.N.; Aditya, K.; Reddy, D.V.
    To minimise the dependence on fossil-fuels, researchers focused on integrating renewable energy with different power electronic inverters. In that process multilevel inverters (MLIs) have gained more attention due to its impeccable advantages. In this work, a novel topology with boost ability, and reduced number of components is proposed. Capacitors used in the proposed structure possess self-balancing ability and the works competently under any loading condition. It is worthy to mention that the blocking voltage of proposed circuit is with in the limits of source voltage even with the dual boost. Sinusoidal pulse width modulation switching strategy technique is employed to get gating signals. Simulation using MATLAB is carried-out to assess the performance of proposed inverter. Further, the proposed circuit is compared with switched-capacitor (SC) based MLIs in terms of number of switches, and standing voltage to highlight the potential merits. © 2020 IEEE.
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    A Novel Switched-Capacitor Boost Multilevel Inverter for PV Applications
    (Institute of Electrical and Electronics Engineers Inc., 2020) Reddy, D.V.; Yellasiri, Y.; Shiva Naik, B.S.; Nageswar Rao, B.N.; Aditya, K.; Bharadwaj, L.
    Nowadays, voltage boosting capability with less part count has become the key feature of recently developed MLI topologies. In this work, a novel topology with boost ability, and reduced number of components is proposed. Capacitors used in the proposed structure possess self-balancing ability and the works competently under any inductive-resistive loading conditions. The blocking voltage of proposed circuit is with in the limits of source voltage even with the dual boost. Sinusoidal pulse width modulation switching strategy technique is employed to get gating signals. Simulation using MATLAB is carried-out and hardware tests are conducted with the available components to assess the performance of proposed inverter. Further, the proposed circuit is compared with switched-capacitor (SC) based MLIs in terms of number of switches, and standing voltage to highlight the potential merits. © 2020 IEEE.
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    A Fault Tolerant Nine-level Inverter Topology with Full DC Utilization for Electric Vehicle Application
    (Institute of Electrical and Electronics Engineers Inc., 2022) Aditya, K.; Yellasiri, Y.; Shiva Naik, B.S.; Nageswar Rao, B.N.
    In this study, a fault-tolerant nine-level inverter architecture for an electric vehicle application is presented. Although the importance of two-level inverters [1] is well-known in EV applications, it contains significant unwanted harmonics for generated voltage. As replacing a two-level inverter proliferates the quality of power with a multilevel inverter, it is considered one of the efficient ways. Even though multilevel inverters' essence considerably reduces total harmonic distortion. Eventually, the size of the filter requirement also will minimize. Because of the increased device count and capacitor voltage balance issues, we have a slew of reliability concerns. As a result, a fault-tolerant nine-level inverter built by cascading H-Bridge [2] and modified T-type voltage source inverters [3] and a bidirectional switch are presented. With the tiniest changes in the switching combinations, the provided inverter topology can sustain system faults caused by the failure of the source and/or switching devices. Subsequently, When compared to standard nine-level inverters, it features fewer switching devices. The results are observed and validated with a hardware platform while the suggested system is simulated in a MATLAB/Simulink environment under standard and malfunctioning settings. © 2022 IEEE
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    A Novel Seven level inverter with Common-Leg Configuration by Employing Transformers
    (Institute of Electrical and Electronics Engineers Inc., 2022) Nageswar Rao, B.; Yellasiri, Y.; Shiva Naik, B.S.; Aditya, K.
    This paper proposes a new multilevel inverter with a common leg structure using three transformers and eight power semiconductor devices. The intended configuration contains of one traditional H-bridge and two half bridges supplied from a single dc source. The switching power circuit powered three transformers with series connections, which produced seven levels (3VDC, 2VDC, VDC, 0, -VDC, -2VDC, -3VDC) at the inverter output from the source VDC. Further, this circuit demonstrates the benefit of fewer switches and drivers in comparison to the traditional circuits for the production of the same load voltage levels. Thus, the suggested topology complexity, volume, and cost are reduced. Finally, the effectiveness of the suggested inverter is performed using MATLAB, and the simulation studies are incorporated. © 2022 IEEE.
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    Performance Analysis of Novel Multilevel Inverter with Minimum Number of Switching Components
    (Institute of Electrical and Electronics Engineers Inc., 2023) Kumar, T.A.; Yellasiri, Y.; Nageswar Rao, B.N.; Aditya, K.; Shiva Naik, B.S.; Karunakaran, E.
    The immense growth in Multilevel inverters are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverters concerning size, rating of switches, filter requirement, and efficiency. According to the current topology, the multilevel inverter employing the bidirectional converter is a DC connection that serves as the bidirectional inverter's input power. The bidirectional inverter is configured to output a voltage with several levels by altering the voltage with the bidirectional converter. Also, because there is no need for a low-frequency transformer or an LC filter at the output stage of the multi-level inverter in the present topology, the frequency does not pose any difficulties. In comparison to other traditional topologies, using an asymmetrical multilevel inverter architecture employs fewer switching components to create greater levels. This study proposes a 27-level multilevel inverter with fewer switching components. To validate the technique, the simulation results are shown. © 2023 IEEE.
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    Novel Nine-level Inverter Topology with Boosting Ability for Electric Vehicle Application
    (Institute of Electrical and Electronics Engineers Inc., 2023) Aditya, K.; Yellasiri, Y.; Shiva Naik, B.S.; Nageswar Rao, B.N.; Karunakaran, E.; Reddy, R.D.
    This paper proposes a new switched-capacitor (SC) based multilevel inverter (MLI) with a boosting gain of four for electric vehicle (EV) applications. The proposed SC-based ninelevel quadruple boost inverter (SC-NLQBI) topology consists of 13 semiconductor switches, three capacitors, and a single input DC supply. It generates nine level voltage waveform, which lessens the requirement for extra filters. Compared to the current nine-level inverter, the new SC-NLQBI topology is simple, compact, and requires fewer parts. Here, a simple triangular carrier signal-based sinusoidal pulse width modulation (SPWM) method is used to generate the required gating pulses. While the proposed topology is being modeled in a MATLAB/Simulation platform using both normal and problematic conditions, the results are analyzed. © 2023 IEEE.
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    Design of a New Single-Phase 15-Level Inverter with Minimized Components
    (Institute of Electrical and Electronics Engineers Inc., 2023) Nageswar Rao, B.N.; Yellasiri, Y.; Shiva Naik, B.S.; Aditya, K.; Karunakaran, E.; Kumar, M.V.
    Multilevel inverters (MLI) provide a number of challenges, the most significant of which is the requirement for a high number of power semiconductors and separate dc supplies to assimilate renewable energy into a grid successfully. Because of this, reducing the number of components used in these kinds of inverters is quite important. Because transformer-based multilevel inverters (TBMIs) have become more commonplace, the use of many dc supplies in the cascaded inverter is no longer necessary for the device to function. Based on the outcomes of this study, a new transformer-based MLI with fifteen levels (15L) and eight switches can be built with only one dc source required. The suggested MLI consists of three isolated transformers. The suggested MLI structure has many unique benefits, including the use of fewer switching components and the availability of self-galvanic isolation. The MATLAB simulation results are carried out to evaluate the effectiveness of the suggested TBMLI. In addition, a comparison of the suggested structure to other recent configurations is presented. © 2023 IEEE.
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    A Fuzzy Logic Based Switching Methodology for a Cascaded H-Bridge Multi-Level Inverter
    (Institute of Electrical and Electronics Engineers Inc., 2019) Azeem, H.; Yellasiri, Y.; Jammala, V.; Shiva Naik, B.S.; Panda, A.K.
    In this letter, an unusual switching technique is implemented using a fuzzy logic approach. The proposed technique simplifies the conventional method by eliminating the traditional logic-gate design. The fuzzy logic pulse generator acts as a lookup table as well as a pulse generator. On the basis of the modulation index as input, controlled membership functions (MFs) and rules of the fuzzy logic controller open various possibilities of producing pulses directly. The proposed technique is evaluated on the cascaded multi-level inverter with symmetric and asymmetric operations using selective harmonic elimination pulsewidth modulation. MFs are designed on the basis of pre-calculated firing conditions for different modulation index values. Hardware verification is carried out to support the proposed switching technique. © 1986-2012 IEEE.