Faculty Publications
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Publications by NITK Faculty
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Item A Switched-Capacitor-Based Multilevel Inverter Topology with Reduced Components(Institute of Electrical and Electronics Engineers Inc., 2018) Sandeep, N.; Yaragatti, U.R.This letter presents an improved sensorless nine-level inverter topology with reduced number of components. It is formed by cascading a three-level T-Type neutral clamped point inverter with a floating capacitor (FC) fed two-level converter unit. Additionally, two line-frequency switches are appended across the dc-link. A simple logic-form equations-based pulse width modulator is designed which is in-charge of maintaining the FC voltage at its reference value without any aid of voltage and current sensor. Thus, the complexity in control of the proposed topology is very minimal. The working principle of the proposed inverter and formulation of logic-form equations is deliberated in detail. Furthermore, experimental results obtained from the developed prototype are presented to validate feasibility and operability of the proposed topology. Finally, a comprehensive comparison with some of the recently reported inverter topologies proving the merits of the proposed topology is included. © 1986-2012 IEEE.Item Switched-Capacitor-Based Quadruple-Boost Nine-Level Inverter(Institute of Electrical and Electronics Engineers Inc., 2019) Sandeep, N.; Jagabar Sathik, J.S.; Yaragatti, U.R.; Krishnasamy, K.This letter describes a novel nine-level inverter based on switched capacitors (SCs) with quadruple-boost ability requiring reduced components. The structure of the proposed topology relies on the series/parallel connection of SCs. It consists of 12 switches and two SCs. As opposed to similar SC-based inverters, the proposed topology does not employ a back-end H-bridge and the voltage stress of all the switches does not exceed twice the input dc voltage. A simple logic-gate-based pulsewidth-modulation scheme is developed for gating the switches of the proposed topology. A comprehensive comparison against the state-of-the-art topologies in terms of the required number of components is performed to attest the outperforming merits of the proposed topology. Finally, various experimental results are presented to validate the feasibility and operability of the proposed topology. © 1986-2012 IEEE.Item A Single DC Source Nine-Level Switched-Capacitor Boost Inverter Topology with Reduced Switch Count(Institute of Electrical and Electronics Engineers Inc., 2020) Siddique, M.D.; Alamri, B.; Salem, F.A.; Orabi, M.; Mekhilef, S.; Shah, N.M.; Sandeep, N.; Jagabar Sathik, J.S.; Iqbal, A.; Ahmed, M.; Ghoneim, S.S.M.; Al-Harthi, M.M.This paper presents a new boost inverter topology with nine level output voltage waveform using a single dc source and two switched capacitors. The capacitor voltages are self-balancing and thus is devoid of any sensors and auxiliary circuitry. The output voltage is twice higher than the input voltage, which eliminates the need for an input dc boost converter especially when the inverter is powered from a renewable source. The merits of the proposed topology in terms of the number of devices and cost are highlighted by comparing the recent and conventional inverter topologies. In addition to this, the total voltage stress of the proposed topology is lower and have a maximum efficiency of 98.25%. The operation and dynamic performance of the proposed topology have been simulated using PLECS software and are validated using an experimental setup considering a different dynamic operation. © 2013 IEEE.Item Seven-level boosting active neutral point clamped inverter using cross-connected switched capacitor cells(Institution of Engineering and Technology jbristow@theiet.org, 2020) Jagabar Sathik, M.J.; Sandeep, N.; Almakhles, D.; Bhatnagar, K.; Yang, Y.; Blaabjerg, F.In this study, an active neutral point clamped-type boosting switched-capacitor multilevel inverter (SCMLI) with selfvoltage balancing capability is proposed. In the proposed topology, a novel switched capacitor cell is used, which has eightswitches and two diodes. The presented topology has reduced power component count with self-boosting and balancingabilities. The distinctive features of the proposed topology are highlighted and benchmarked against other recent 7L-SCMLItopologies. To validate the feasibility of the proposed topology, experimental tests are performed on a 1 kW prototype hardwaresetup. © 2020 The Institution of Engineering and Technology.