Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
5 results
Search Results
Item Single-phase seven-level grid-connected photovoltaic system with ripple correlation control maximum power point tracking(International Journal of Renewable Energy Research, 2016) Sandeep, N.; Yaragatti, R.Y.This paper puts forward a control scheme for single-phase photovoltaic (PV) fed grid connected with cascade Hbridge (CHB) inverter. A unique control strategy based on the voltage ratio is proposed and is embedded with ripple correlation control (RCC) based maximum power point tracking (MPPT) to ensure the efficient energy conversion. The control scheme employed enables the independent operation and control of individual DC link voltage, ensuring the extraction of maximum power available from each PV panel. In addition, low harmonic grid currents are generated with an arbitrary power factor. Independent control of active and reactive power is exercised by decoupled component method. Numerical simulation was performed using the MATLAB/SIMULINK platform and results for three H-bridge cells connected in series are presented to support the theoretical concepts and control scheme proposed.Item Operation and Control of a Nine-Level Modified ANPC Inverter Topology with Reduced Part Count for Grid-Connected Applications(Institute of Electrical and Electronics Engineers Inc., 2018) Sandeep, N.; Yaragatti, U.R.This paper presents a nine-level active-neutral-point-clamped (ANPC) based multilevel inverter (MLI) topology for grid-connected applications requiring only ten switches. The envisaged structure comprises two parts, namely five-level ANPC unit, and a two-level converter leg whose midpoint is used as another ac terminal. An ad hoc switching state redundancy based modulation strategy is used to ensure that the voltage across the flying capacitor is tightly balanced and is implemented using a look-up table further simplifies the control complexity. The performance and effectiveness of the proposed topology with its control scheme are validated through simulations and experimental tests. Comparison with other MLIs is included to highlight the merits of the proposed topology. From the results, it will be shown that the proposed inverter requires the least part count as compared to other topologies with the same performance and output quality. © 1982-2012 IEEE.Item A Switched-Capacitor-Based Multilevel Inverter Topology with Reduced Components(Institute of Electrical and Electronics Engineers Inc., 2018) Sandeep, N.; Yaragatti, U.R.This letter presents an improved sensorless nine-level inverter topology with reduced number of components. It is formed by cascading a three-level T-Type neutral clamped point inverter with a floating capacitor (FC) fed two-level converter unit. Additionally, two line-frequency switches are appended across the dc-link. A simple logic-form equations-based pulse width modulator is designed which is in-charge of maintaining the FC voltage at its reference value without any aid of voltage and current sensor. Thus, the complexity in control of the proposed topology is very minimal. The working principle of the proposed inverter and formulation of logic-form equations is deliberated in detail. Furthermore, experimental results obtained from the developed prototype are presented to validate feasibility and operability of the proposed topology. Finally, a comprehensive comparison with some of the recently reported inverter topologies proving the merits of the proposed topology is included. © 1986-2012 IEEE.Item A Self-Balancing Five-Level Boosting Inverter with Reduced Components(Institute of Electrical and Electronics Engineers Inc., 2019) Sandeep, N.; Jagabar Sathik, J.S.; Yaragatti, U.R.; Krishnasamy, K.Two-Stage boosting multilevel inverters (MLIs), which are highly suitable for photovoltaic power plants, are known to suffer because of the high voltage stress on the switches of second stage. One of the ways to confront this issue is through eliminating the front-end booster. However, this leads to increased structural and control complexity of the resulting integrated boosting MLI. This letter presents a single-stage boosting MLI requiring lesser number of switches, diodes, and capacitors for renewable power generation applications. It requires nine switches and only one capacitor for five-level voltage generation. The topology has inherent self-balancing capability, thereby does not need additional balancing circuitry. The proposed topology has a uniform peak inverse voltage stress on the switches of value equal to the input dc voltage. A less complicated logic-form-equations-based gating pulse generation scheme is designed for enabling the proposed MLI to maintain its capacitor voltage. Further, a comparative study with state-of-the-art topologies is carried out to demonstrate the superior performance of the proposed topology. Finally, the feasibility of the proposed topology is validated through experimental tests and the corresponding results are elucidated. © 1986-2012 IEEE.Item Switched-Capacitor-Based Quadruple-Boost Nine-Level Inverter(Institute of Electrical and Electronics Engineers Inc., 2019) Sandeep, N.; Jagabar Sathik, J.S.; Yaragatti, U.R.; Krishnasamy, K.This letter describes a novel nine-level inverter based on switched capacitors (SCs) with quadruple-boost ability requiring reduced components. The structure of the proposed topology relies on the series/parallel connection of SCs. It consists of 12 switches and two SCs. As opposed to similar SC-based inverters, the proposed topology does not employ a back-end H-bridge and the voltage stress of all the switches does not exceed twice the input dc voltage. A simple logic-gate-based pulsewidth-modulation scheme is developed for gating the switches of the proposed topology. A comprehensive comparison against the state-of-the-art topologies in terms of the required number of components is performed to attest the outperforming merits of the proposed topology. Finally, various experimental results are presented to validate the feasibility and operability of the proposed topology. © 1986-2012 IEEE.