Faculty Publications

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Publications by NITK Faculty

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Author: search.filters.author.Rekha, S.Subject: search.filters.subject.Analog to digital conversion

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    A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique
    (Birkhauser, 2020) Polineni, P.; Bhat, M.S.; Rekha, S.
    In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of 568?m×298?m and consumes a power as less as 0.28?W. It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/? 0.84 least significant bit (LSB) and + 0.1/? 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.
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    A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications
    (John Wiley and Sons Inc, 2021) Polineni, S.; Rekha, S.; Bhat, M.S.
    A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 ?W across target resolutions (8–15 bits). © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.