Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
Search Results
Item Fourier Series-Based Analytical Model for Channel Potential of Dual Material Gate SOI Junctionless FinFET(Springer, 2025) Mathew, S.; Rao, R.In this article, a robust Fourier series based analytical model for channel potential is derived for a Dual Material Gate Junctionless Fin Field Effect Transistor (DMG JLFinFET) on a Silicon-On-Insulator (SOI) substrate. For most of the regions in the cuboidal channel, especially at the location where the onset of current conduction happens, the channel potential model developed in this work matches very well with the potential obtained from TCAD simulations. The analytical model presented in this article is capable of calculating the channel potential of the DMG JLFinFETs for most of the channel region, considering various device parameters such as channel length, fin height, and fin width, with a maximum deviation of 0.07 V. However, for channel regions very close to buried oxide, the channel potential model over-predicts potential obtained through simulation by around 0.1 V. In most of the cases of varying device parameters, the Fourier series-based potential model developed in this work accurately predicts channel potential at the location of the onset of current conduction. Hence, it can be used to model various device parameters such as threshold voltage and sub-threshold swing. © The Minerals, Metals & Materials Society 2025.Item Investigation of the impact of gate oxide thickness variation of Junction-less FinFET using BSIM-CMG model for LIF neuron and STDP circuit application(Institute of Physics, 2025) Vinaya, S.J.; Rao, R.; Nikhil, K.S.In neuromorphic circuits, Leaky Integrate-and-Fire (LIF) neuron and Spike-Timing-Dependent Plasticity (STDP) circuits are very much essential. These circuits are significantly influenced by the characteristics of the transistors used in their design. In this work, the impact of gate oxide thickness variation on the performance of FinFET-based neuromorphic circuits using the (Berkeley Short-channel IGFET Model—Common Multi-Gate) BSIM-CMG model is investigated. TCAD simulations are carried out to analyze the electrical characteristics of FinFETs with varying oxide thicknesses. The circuit-level simulations are carried out using Cadence tool to evaluate their impact on synaptic weight updates in STDP and LIF neuron operation and circuits. The results show that reducing the gate oxide thickness from 5 nm to 2 nm enhances the capacitor voltage response, thereby improving charge storage and synaptic weight modulation. It has been shown that there is a consistent increase in capacitor voltage as oxide thickness decreases, which directly impacts the learning efficiency of STDP circuits. Varying oxide thickness will also impact on firing frequency of LIF neuron circuit.These results signifies performances of STDP and LIF neuron circuits for neuromorphic applications. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.