Faculty Publications
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Item A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding(Elsevier B.V., 2020) Girija Sravani, K.; Rao, R.This paper details a novel asynchronous pipelining methodology that maximizes the throughput buffering capacity and robustness of gate-level pipelined systems. The data paths in the proposed pipeline style are encoded using hybrid logic encoding scheme, which incorporates simplicity of the single-rail encoding and robustness of the dual-rail encoding. The control path that provides the synchronization between pipeline stages is constructed based on the simple and high-speed early acknowledgment protocol. Further, the proposed pipeline accommodates isolate phase to achieve 100% storage capacity. Two test cases: A 4-bit,10-stage FIFO and a 16-bit adder, have been designed in 90 nm technology to validate the proposed pipeline style. The FIFO has been laid out in the UMC 180 nm process using the cadence tool suite. The post-layout results of FIFO show 12.5% better throughput than the high capacity single-rail pipeline. Simulation results of the adder also reveal that the proposed structure achieves the throughput of 3.44 Giga-items/sec, which is 44.18% higher than the APCDP (Asynchronous pipeline based on constructed critical path) and 11.9% higher than the high capacity single-rail pipelines. © 2019 Elsevier B.V.Item Design of Dual-Material Gate Junctionless FinFET based on the Properties of Materials Forming Gate Electrode(Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.This work elaborately investigates the electrical behaviour and short channel performance of Dual-Material Gate Junctionless Fin Field Effect Transistors (DMG-JLFinFETs) with multiple-gate metal pairs and varying gate metal length ratios. Rigorous analysis on the nature of DMG-JLFinFET with gate length as low as 10 nm is done using a device simulator by Silvaco, Inc. The gate material closer to the source, namely M1, has a dominating influence on the threshold voltage (Vth) and tunnelling current (Itunn) than the gate material closer to the drain (named M2) in a DMG-JLFinFET. Itunn is lower when the work function of M1 (ΦM1) is greater than the work function of M2 (ΦM2). The relative change in threshold voltage is minimum for Platinum–Gold (PtAu)-DMG-JLFinFET (0.68%). Titanium–Aluminium (TiAl) and Nickel–Titanium (NiTi) gate material pairs, having the same work function difference of 0.38 eV, have the least Drain-Induced Barrier Lowering (DIBL) of 12.88 mV/V. A better Sub-threshold Swing (SS) is observed for DMG-JLFinFET having ΦM1 < ΦM2. For devices with ΦM1 > ΦM2, SS can be improved by making a length of M1 (LM1) greater than 70% of the total gate length (Lg). © 2024 IETE.Item Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems(Springer, 2024) Saranya, M.N.; Rao, R.The increasing multi-core system complexity with technology scaling introduces new constraints and challenges to interconnection network design. Consequently, the research community has a converging trend toward an asynchronous design paradigm for Network-on-Chip (NoC) architecture as a promising solution to these challenges. This paper addresses the design and functional verification aspects of an asynchronous NoC router microarchitecture for a Globally Asynchronous Locally Synchronous (GALS) system. Firstly, the paper introduces a novel mixed-level abstract simulation approach for faster functional verification of the asynchronous architecture using the commercially available Spectre Analog and mixed-signal simulation (AMS) Designer tool. This simulation methodology intends to ensure the feasibility of the design and identify shortcomings, if any, before the subsequent implementation stages of the design. Also, the paper proposes a new baseline asynchronous router built on a domino logic pipeline template with a novel hybrid encoding scheme. The new hybrid encoding scheme facilitates simple architecture with no additional timing constraints. The proposed verification methodology evaluates the baseline asynchronous router’s functional verification in Cadence’s AMS designer tool. Preliminary simulation results conform to the objectives of the paper. Further, the same verification setup establishes the design validation in subsequent stages of the design implementation. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.