Faculty Publications

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Author: search.filters.author.Rajesh Shetty, K.Subject: search.filters.subject.Memory architecture

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    Design and construction of BCH codes for enhancing data integrity in multi level flash memories
    (Inderscience Publishers, 2012) Rajesh Shetty, K.; Ramakrishna, K.; Prashantha Kumar, H.; Sripati, U.
    Flash memories have found extensive application for use in storage devices. The storage capacity and reliability of these devices have increased enormously over the years. With increase in density of data storage, the raw bit error rate (RBER), associated with the storage device increases. Error control coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes for flash memories based on multi level cell (MLC) concept. This is in continuation of our work on synthesis of BCH codes for improving the performance of flash memories based on single level cells (SLC). The improvement in device integrity resulting from the use of these codes has been quantified in this paper along with computation of parameters which allows modelling of flash memory as an equivalent channel. While synthesising codes, we have adhered to the limitations imposed by the memory architecture. Use of these codes in storage devices will result in considerable enhancement of device reliability and consequently open up many new applications for this class of storage devices. © 2012 Inderscience Enterprises Ltd.
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    Enhancing the error-correcting capability of imai-kamiyanagi codes for data storage systems by adopting iterative decoding using a parity check tree
    (2012) Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Shankarananda, B.
    A novel low-complexity, soft decision technique which allows the decoding of distance-5 double error-correcting Imai-Kamiyanagi codes by using a parity check tree associated with the Tanner graph is proposed. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. For the AWGN channel, gains in excess of 1.5 dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (46, 32), (81, 64), and (148, 128) shortened Imai-Kamiyanagi codes. Copyright © 2012 by the IETE.