Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
2 results
Search Results
Item Synthesis of BCH codes for enhancing data integrity in flash memories(2010) Rajesh Shetty, K.; Sripati, U.; Prashantha Kumar, H.; Shankarananda, B.Flash memories have found extensive application for use in portable storage devices. They have been used for code storage as well as data storage. The storage density associated with these devices has increased tremendously in the past few years. This has necessitated very dense packing of data bits on the device. This gives rise to increased Raw Bit Error Rate (RBER) as a result of Inter Symbol Interference (ISI) between bits stored in adjacent cells. This necessitates the use of powerful error control codes to guarantee information integrity. With the increase in density of data storage, the raw bit error rate (RBER) associated with the storage device increases. Error Control Coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes based on memory models proposed by the semiconductor industry. These codes have better error correcting capability than the codes used in current practice. ©2010 IEEE.Item Design and construction of BCH codes for enhancing data integrity in multi level flash memories(Inderscience Publishers, 2012) Rajesh Shetty, K.; Ramakrishna, K.; Prashantha Kumar, H.; Sripati, U.Flash memories have found extensive application for use in storage devices. The storage capacity and reliability of these devices have increased enormously over the years. With increase in density of data storage, the raw bit error rate (RBER), associated with the storage device increases. Error control coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes for flash memories based on multi level cell (MLC) concept. This is in continuation of our work on synthesis of BCH codes for improving the performance of flash memories based on single level cells (SLC). The improvement in device integrity resulting from the use of these codes has been quantified in this paper along with computation of parameters which allows modelling of flash memory as an equivalent channel. While synthesising codes, we have adhered to the limitations imposed by the memory architecture. Use of these codes in storage devices will result in considerable enhancement of device reliability and consequently open up many new applications for this class of storage devices. © 2012 Inderscience Enterprises Ltd.