Faculty Publications
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Publications by NITK Faculty
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Item A Three-Stage Operational Transconductance Amplifier for Delta Sigma Modulator(Institute of Electrical and Electronics Engineers Inc., 2018) Aparna, T.; Polineni, S.; Bhat, M.S.The design and simulation of a low power, high gain three stage operational transconductance amplifier (OTA) is presented. This OTA has a DC gain of 73.5 dB, a unity gain bandwidth (UGB) of 39.8 MHz and a phase margin of 59°. The total power consumed by OTA is 332 μW. The DC gain and the power dissipation parameters of the OTA are found to be better than the previously published results of [1]-[4]. Further, a first order Delta Sigma Modulator (DSM) is designed as a vehicle to test the OTA by integrating it with a comparator and a DAC for a signal bandwidth of 2 kHz with an oversampling ratio (OSR) of 250 for low frequency biomedical applications. All the blocks are designed using UMC 180nm CMOS 1P9M technology, with 1.8 V supply voltage. The simulation results show that the in-band signal to noise and distortion ratio (SNDR) of the DSM is 53 dB, which is equivalent to 8.5 effective number of bits (ENOB). © 2018 IEEE.Item 91dB dynamic range 9.5nW low pass filter for bio-medical applications(IEEE Computer Society help@computer.org, 2018) Jayaram Reddy, M.K.; Polineni, S.; Laxminidhi, L.This paper presents a second order, fully differential, low pass filter. The filter has a tunable bandwidth in the range 4 Hz to 100 Hz and offers a dynamic range of 91 dB. The filter is based on the source-follower biquad operating in the sub-Threshold region. The main idea is to exploit the strengths of sub-Threshold source follower circuit, like low noise, low output impedance, high linearity and low power. The filter design has been validated in UMC 0.18 um CMOS process. The filter consumes only 9.5 nW of power at 1.8 V supply, making it suitable for bio-medical applications. In terms of noise and dynamic range the reported filter is better than previous works found from the literature. © 2018 IEEE.Item Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology(Institute of Electrical and Electronics Engineers Inc., 2019) Bonthala, S.; Uppoor, Y.; Nayak, A.; Polineni, S.; Bhat, M.S.This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V. © 2019 IEEE.Item A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique(Springer Verlag, 2019) Polineni, S.; Bhat, M.S.; Rajan, A.A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology. © 2018, King Fahd University of Petroleum & Minerals.Item A 0.3?V, 56?dB DR, 100?Hz fourth order low-pass filter for ECG acquisition system(Elsevier Ltd, 2019) Polineni, S.; Hanumantha Rao, G.; Rekha, S.; Bhat, M.S.This paper proposes an extremely low voltage, low power bulk-driven voltage follower (BD-VF). As an application of the proposed BD-VF, a 4th order low-pass filter (LPF) with cutoff frequency adjustable from 50 Hz to 250 Hz is designed for electrocardiogram (ECG) acquisition systems. The filter is implemented in UMC 180 nm CMOS technology occupying only 0.03 mm2 area. Post layout simulation results show that the filter offers 56 dB dynamic range even with an extremely low supply voltage of 0.3 V. The total power consumption of the filter is 4.8 nW for a cutoff frequency of 100 Hz. The Figure-of-merit (FoM) and capacitance/pole of the filter are 5.7 × 10?15 and 2.2 pF respectively. The proposed filter offers the lowest FoM compared to the state-of-the-art nW-class filters. © 2019 Elsevier LtdItem A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications(John Wiley and Sons Inc, 2021) Polineni, S.; Rekha, S.; Bhat, M.S.A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 ?W across target resolutions (8–15 bits). © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.