Faculty Publications

Now showing 1 - 3 of 3

LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
(Association for Computing Machinery acmhelp@acm.org, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
An FPGA-based Network-on-Chip (NoC) using a low-latency router with a look-ahead bypass (LBNoC) is discussed in this article. The proposed design targets the optimized area with improved network performance. The techniques such as single-cycle router bypass, adaptive routing module, parallel Virtual Channel (VC), and Switch allocation, combined virtual cut through and wormhole switching, have been employed in the design of the LBNoC router. The LBNoC router is parameterizable with the network topology, traffic patterns, routing algorithms, buffer depth, buffer width, number of VCs, and I/O ports being configurable. A table-based routing algorithm has been employed to support the design of custom topologies. The input buffer modules of NoC router have been mapped on the FPGA Block RAM hard blocks to utilize resources efficiently. The LBNoC architecture consumes 4.5% and 27.1% fewer hardware resources than the ProNoC and CONNECT NoC architectures. The average packet latency of the LBNoC NoC architecture is 30% and 15% lower than the CONNECT and ProNoC architectures. The LBNoC architecture is 1.15× and 1.18× faster than the ProNoC and CONNECT NoC frameworks. © 2020 Association for Computing Machinery.
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA
(Springer, 2020) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.
The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall performance of CMPs and MPSoCs significantly. We propose P-NoC: an FPGA-based parameterized framework for analyzing the performance of NoC architectures based on various design decision parameters in this paper. The mesh and a multi-local port mesh (ML-mesh) topologies have been considered for the study. By fine-tuning various NoC parameters and synthesizing on the FPGA, identify that the performance of NoC architectures are influenced by the configuration of router parameters and the interconnect. Experiments show that the flit width, buffer depth, virtual channels parameters have a significant impact on the FPGA resources. We analyze the performance of the NoCs on six traffic patterns viz., uniform, bit shuffle, random permutation, transpose, bit complement and nearest neighbor. Configuring the router and the interconnect parameters, the ML-mesh topology yields 75% lesser utilization of FPGA resources compared to the mesh. The ML-mesh topology shows an improvement of 33.2% in network latency under localized traffic pattern. The mesh and ML-mesh topologies have 0.53× and 0.1× higher saturation throughput under nearest neighbor traffic compared to uniform random traffic. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.
FPGA friendly NoC simulation acceleration framework employing the hard blocks
(Springer, 2021) Prasad, B.M.P.; Parane, K.; Talawar, B.
A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become the vehicle for simulation acceleration due to the properties of parallelism. Most of the state-of-the-art FPGA based NoC simulators utilize soft logic only for modeling the NoCs, leaving out the hard blocks to be unutilized. In this work, the FIFO Buffer and Crossbar switch functionalities of the NoC router have been embedded in the Block RAM (BRAMs) and the DSP48E1 slices with large multiplexer respectively. Employing the proposed techniques of mapping the NoC router components on the FPGA hard blocks, an NoC simulation acceleration framework based on the FPGA is presented in this work. A huge reduction in the use of the Configurable Logic Blocks (CLBs) has been observed when the FIFO buffer and Crossbar components of the NoC topology’s router micro-architecture are embedded in FPGA hard blocks. Our experimental results show that the topologies implemented employing the proposed FPGA friendly mapping of the NoC router components on the hard blocks consume 43.47% fewer LUTs and 41.66% fewer FFs than the topologies with CLB implementation. To optimize the latency of the NoC under consideration, a control unit called “buf_empty_checker” has been employed. A reduction in average latency has been observed compared to the CLB based topology implementation employing the proposed mapping. The proposed work consumes 10.88% fewer LUTs than the CONNECT NoC generation tool. Compared to DART, a reduction of 73.38% and 66.55% in LUTs and FFs has been observed with respect to the proposed work. The average packet latency of the proposed NoC architecture is 24.8% and 19.1% lesser than the CONNECT and DART architectures. © 2021, The Author(s), under exclusive licence to Springer-Verlag GmbH, AT part of Springer Nature.

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